lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <f839a280-aa76-4963-9580-a6e089136bb5@quicinc.com>
Date: Tue, 17 Dec 2024 15:50:47 +0800
From: Jinlong Mao <quic_jinlmao@...cinc.com>
To: Suzuki K Poulose <suzuki.poulose@....com>,
        Mike Leach
	<mike.leach@...aro.org>, James Clark <james.clark@....com>,
        Alexander
 Shishkin <alexander.shishkin@...ux.intel.com>,
        Andy Gross
	<agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Rob Herring
	<robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
	<conor+dt@...nel.org>
CC: <linux-kernel@...r.kernel.org>, <coresight@...ts.linaro.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>
Subject: Re: [PATCH v1 0/2] Add Qualcomm extended CTI support



On 2024/10/10 17:49, Jinlong Mao wrote:
> 
> 
> On 2024/9/3 20:18, Mao Jinlong wrote:
>> The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI.
>> It allows a debugger to send to trigger events to a processor or to send
>> a trigger event to one or more processors when a trigger event occurs on
>> another processor on the same SoC, or even between SoCs.
>>
>> QCOM extended CTI supports up to 128 triggers. And some of the register
>> offsets are changed.
>>
>> The commands to configure CTI triggers are the same as ARM's CTI.
>>
> 
> Hi Reviewers,
> 
> Could you please help to provide some comments from the design point of 
> view for the changes ?
> 
> The main difference of extended CTI to the normal CTI is that the
> address mapping is changed and it supports a max of 128 trigger signals.
> 
> On one soc, there will be both normal arm CTIs and QCOM extended CTIs.
> 
> As max trigger number becomes 128. So triger registers becomes 4.
> 
> Like CTITRIGINSTATUS  --- > CTITRIGINSTATUS_EXTENDED(n)     (0x040 + (4 
> * n))  n is 0 to 4.
> 
> Thanks
> Jinlong Mao

Gentle reminder for the review from the code design point of view.

> 
>> Mao Jinlong (2):
>>    dt-bindings: arm: Add Qualcomm extended CTI
>>    coresight: cti: Add Qualcomm extended CTI support
>>
>>   .../bindings/arm/arm,coresight-cti.yaml       |  14 ++
>>   .../hwtracing/coresight/coresight-cti-core.c  |  75 +++++++----
>>   .../coresight/coresight-cti-platform.c        |  16 ++-
>>   .../hwtracing/coresight/coresight-cti-sysfs.c | 124 ++++++++++++++----
>>   drivers/hwtracing/coresight/coresight-cti.h   | 123 +++++++++++------
>>   5 files changed, 253 insertions(+), 99 deletions(-)
>>
> 


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ