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Message-ID: <20241217092636.17482-1-quic_pbrahma@quicinc.com>
Date: Tue, 17 Dec 2024 14:56:36 +0530
From: Pratyush Brahma <quic_pbrahma@...cinc.com>
To: <andersson@...nel.org>
CC: <konradybcio@...nel.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>, <linux-arm-msm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
Pratyush Brahma
<quic_pbrahma@...cinc.com>
Subject: [PATCH] arm64: dts: qcom: qcs8300: Update memory map
This is based on Jingyi Wang's patches [1] to introduce the
initial dtsi for QCS8300 SOC.
New updates to the memory map of qcs8300 have brought in some
new carveouts (viz. sail_ss, firmware memory, tz memory, etc.) and
also the base addresses of some of the pil carveouts (q6_cdsp_dtb_mem
and cdsp_mem) have changed.
Incorporate these changes in the new memory map for qcs8300. Also
modify the labels of some of the carveouts to indicate pil carveouts.
[1] https://lore.kernel.org/all/20240925-qcs8300_initial_dtsi-v2-3-494c40fa2a42@quicinc.com/
Signed-off-by: Pratyush Brahma <quic_pbrahma@...cinc.com>
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 180 ++++++++++++++++++++++++--
1 file changed, 170 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 2c35f96c3f28..e16d11c05515 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -377,6 +377,21 @@
#size-cells = <2>;
ranges;
+ sail_ss_mem: sail-ss-region@...00000 {
+ reg = <0x0 0x80000000 0x0 0x10000000>;
+ no-map;
+ };
+
+ hyp_mem: hyp-region@...00000 {
+ reg = <0x0 0x90000000 0x0 0x600000>;
+ no-map;
+ };
+
+ xbl_boot_mem: xbl-boot-region@...00000 {
+ reg = <0x0 0x90600000 0x0 0x200000>;
+ no-map;
+ };
+
aop_image_mem: aop-image-region@...00000 {
reg = <0x0 0x90800000 0x0 0x60000>;
no-map;
@@ -388,6 +403,26 @@
no-map;
};
+ uefi_logs_mem: uefi-logs-region@...b0000 {
+ reg = <0x0 0x908b0000 0x0 0x10000>;
+ no-map;
+ };
+
+ ddr_training_checksum_data_mem: ddr-training-checksum-data-region@...c0000 {
+ reg = <0x0 0x908c0000 0x0 0x1000>;
+ no-map;
+ };
+
+ reserved_mem: reserved-region@...f0000 {
+ reg = <0x0 0x908f0000 0x0 0xe000>;
+ no-map;
+ };
+
+ secdata_apps_mem: secdata-apps-region@...fe000 {
+ reg = <0x0 0x908fe000 0x0 0x2000>;
+ no-map;
+ };
+
smem_mem: smem@...00000 {
compatible = "qcom,smem";
reg = <0x0 0x90900000 0x0 0x200000>;
@@ -395,6 +430,61 @@
hwlocks = <&tcsr_mutex 3>;
};
+ tz_sail_mailbox_mem: tz-sail-mailbox-region@...00000 {
+ reg = <0x0 0x90c00000 0x0 0x100000>;
+ no-map;
+ };
+
+ sail_mailbox_mem: sail-mailbox-region@...00000 {
+ reg = <0x0 0x90d00000 0x0 0x100000>;
+ no-map;
+ };
+
+ sail_ota_mem: sail-ota-region@...00000 {
+ reg = <0x0 0x90e00000 0x0 0x300000>;
+ no-map;
+ };
+
+ xbl_dtlog_mem: xbl-dtlog-region@...40000 {
+ reg = <0x0 0x91a40000 0x0 0x40000>;
+ no-map;
+ };
+
+ gunyah_md_mem: gunyah-md-region@...80000 {
+ reg = <0x0 0x91a80000 0x0 0x80000>;
+ no-map;
+ };
+
+ aoss_backup_mem: aoss-backup-region@...00000 {
+ reg = <0x0 0x91b00000 0x0 0x40000>;
+ no-map;
+ };
+
+ cpucp_backup_mem: cpucp-backup-region@...40000 {
+ reg = <0x0 0x91b40000 0x0 0x40000>;
+ no-map;
+ };
+
+ tz_config_backup_mem: tz-config-backup-region@...80000 {
+ reg = <0x0 0x91b80000 0x0 0x10000>;
+ no-map;
+ };
+
+ ddr_training_data_mem: ddr-training-data-region@...90000 {
+ reg = <0x0 0x91b90000 0x0 0x10000>;
+ no-map;
+ };
+
+ cdt_data_backup_mem: cdt-data-backup-region@...a0000 {
+ reg = <0x0 0x91ba0000 0x0 0x1000>;
+ no-map;
+ };
+
+ tzffi_mem: tzffi-region@...00000 {
+ reg = <0x0 0x91c00000 0x0 0x1400000>;
+ no-map;
+ };
+
lpass_machine_learning_mem: lpass-machine-learning-region@...00000 {
reg = <0x0 0x93b00000 0x0 0xf00000>;
no-map;
@@ -405,12 +495,12 @@
no-map;
};
- camera_mem: camera-region@...00000 {
+ camera_mem: pil-camera-region@...00000 {
reg = <0x0 0x95200000 0x0 0x500000>;
no-map;
};
- adsp_mem: adsp-region@...00000 {
+ adsp_mem: pil-adsp-region@...00000 {
no-map;
reg = <0x0 0x95c00000 0x0 0x1e00000>;
};
@@ -425,35 +515,105 @@
no-map;
};
- gpdsp_mem: gpdsp-region@...00000 {
+ gpdsp_mem: pil-gpdsp-region@...00000 {
reg = <0x0 0x97b00000 0x0 0x1e00000>;
no-map;
};
- q6_cdsp_dtb_mem: q6-cdsp-dtb-region@...00000 {
- reg = <0x0 0x99900000 0x0 0x80000>;
+ q6_cdsp_dtb_mem: q6-cdsp-dtb-region@...00000 {
+ reg = <0x0 0x9b700000 0x0 0x80000>;
no-map;
};
- cdsp_mem: cdsp-region@...80000 {
- reg = <0x0 0x99980000 0x0 0x1e00000>;
+ cdsp_mem: pil-cdsp-region@...00000 {
+ reg = <0x0 0x99900000 0x0 0x1e00000>;
no-map;
};
- gpu_microcode_mem: gpu-microcode-region@...80000 {
+ gpu_microcode_mem: pil-gpu-region@...80000 {
reg = <0x0 0x9b780000 0x0 0x2000>;
no-map;
};
- cvp_mem: cvp-region@...82000 {
+ cvp_mem: pil-cvp-region@...82000 {
reg = <0x0 0x9b782000 0x0 0x700000>;
no-map;
};
- video_mem: video-region@...82000 {
+ video_mem: pil-video-region@...82000 {
reg = <0x0 0x9be82000 0x0 0x700000>;
no-map;
};
+
+ audio_mdf_mem: audio-mdf-region@...00000 {
+ reg = <0x0 0xae000000 0x0 0x1000000>;
+ no-map;
+ };
+
+ firmware_mem: firmware-region@...00000 {
+ reg = <0x0 0xb0000000 0x0 0x800000>;
+ no-map;
+ };
+
+ hyptz_reserved_mem: hyptz-reserved@...00000 {
+ reg = <0x0 0xbeb00000 0x0 0x11500000>;
+ no-map;
+ };
+
+ firmware_scmi_mem: scmi-region@...00000 {
+ reg = <0x0 0xd0000000 0x0 0x40000>;
+ no-map;
+ };
+
+ firmware_logs_mem: firmware-logs-region@...40000 {
+ reg = <0x0 0xd0040000 0x0 0x10000>;
+ no-map;
+ };
+
+ firmware_audio_mem: firmware-audio-region@...50000 {
+ reg = <0x0 0xd0050000 0x0 0x4000>;
+ no-map;
+ };
+
+ firmware_reserved_mem: firmware-reserved-region@...54000 {
+ reg = <0x0 0xd0054000 0x0 0x9c000>;
+ no-map;
+ };
+
+ firmwarequantum_test_mem: firmwarequantum-test-region@...f0000 {
+ reg = <0x0 0xd00f0000 0x0 0x10000>;
+ no-map;
+ };
+
+ tags_mem: tags-region@...00000 {
+ reg = <0x0 0xd0100000 0x0 0x800000>;
+ no-map;
+ };
+
+ qtee_mem: qtee-region@...00000 {
+ reg = <0x0 0xd1300000 0x0 0x500000>;
+ no-map;
+ };
+
+ deep_sleep_back_up_mem: deep-sleep-back-up-region@...00000 {
+ reg = <0x0 0xd1800000 0x0 0x100000>;
+ no-map;
+ };
+
+ trusted_apps_mem: trusted-apps-region@...00000 {
+ reg = <0x0 0xd1900000 0x0 0x1900000>;
+ no-map;
+ };
+
+ tz_stat_mem: tz-stat-region@...00000 {
+ reg = <0x0 0xdb100000 0x0 0x100000>;
+ no-map;
+ };
+
+ cpucp_fw_mem: cpucp-fw-region@...00000 {
+ reg = <0x0 0xdb200000 0x0 0x100000>;
+ no-map;
+ };
};
smp2p-adsp {
--
2.17.1
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