| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20241217100359.4017214-5-quic_varada@quicinc.com>
Date: Tue, 17 Dec 2024 15:33:58 +0530
From: Varadarajan Narayanan <quic_varada@...cinc.com>
To: <bhelgaas@...gle.com>, <lpieralisi@...nel.org>, <kw@...ux.com>,
<manivannan.sadhasivam@...aro.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>, <vkoul@...nel.org>,
<kishon@...nel.org>, <andersson@...nel.org>, <konradybcio@...nel.org>,
<p.zabel@...gutronix.de>, <quic_varada@...cinc.com>,
<quic_nsekar@...cinc.com>, <dmitry.baryshkov@...aro.org>,
<quic_srichara@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
<linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-phy@...ts.infradead.org>
CC: Praveenkumar I <quic_ipkumar@...cinc.com>
Subject: [PATCH v3 4/5] arm64: dts: qcom: ipq5332: Add PCIe related nodes
From: Praveenkumar I <quic_ipkumar@...cinc.com>
Add phy and controller nodes for pcie0_x1 and pcie1_x2.
Signed-off-by: Praveenkumar I <quic_ipkumar@...cinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@...cinc.com>
---
v3: Fix compatible string for phy nodes
Use ipq9574 as backup compatible instead of new compatible for ipq5332
Fix mixed case hex addresses
Add "mhi" space
Removed unnecessary comments and stray blank lines
v2: Fix nodes' location per address
---
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 212 +++++++++++++++++++++++++-
1 file changed, 210 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index d3c3e215a15c..add5d50b5fb0 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -186,6 +186,46 @@ rng: rng@...00 {
clock-names = "core";
};
+ pcie0_phy: phy@...000{
+ compatible = "qcom,ipq5332-uniphy-gen3x1-pcie-phy";
+ reg = <0x004b0000 0x800>;
+
+ clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
+
+ resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>;
+ reset-names = "phy",
+ "phy_ahb",
+ "phy_cfg";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie0_pipe_clk_src";
+
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ pcie1_phy: phy@...000 {
+ compatible = "qcom,ipq5332-uniphy-gen3x2-pcie-phy";
+ reg = <0x004b1000 0x1000>;
+
+ clocks = <&gcc GCC_PCIE3X2_PIPE_CLK>,
+ <&gcc GCC_PCIE3X2_PHY_AHB_CLK>;
+
+ resets = <&gcc GCC_PCIE3X2_PHY_BCR>,
+ <&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>;
+ reset-names = "phy",
+ "phy_ahb";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie1_pipe_clk_src";
+
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
tlmm: pinctrl@...0000 {
compatible = "qcom,ipq5332-tlmm";
reg = <0x01000000 0x300000>;
@@ -212,8 +252,8 @@ gcc: clock-controller@...0000 {
#interconnect-cells = <1>;
clocks = <&xo_board>,
<&sleep_clk>,
- <0>,
- <0>,
+ <&pcie1_phy>,
+ <&pcie0_phy>,
<0>;
};
@@ -364,6 +404,174 @@ usb_dwc: usb@...0000 {
};
};
+ pcie0: pcie@...00000 {
+ compatible = "qcom,pcie-ipq9574";
+ reg = <0x00080000 0x3000>,
+ <0x20000000 0xf1d>,
+ <0x20000f20 0xa8>,
+ <0x20001000 0x1000>,
+ <0x20100000 0x1000>,
+ <0x00083000 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0 0x20200000 0x20200000 0 0x00100000>,
+ <0x02000000 0 0x20300000 0x20300000 0 0x0fd00000>;
+
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 36 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 37 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 38 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE3X1_0_AXI_M_CLK>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_CLK>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE3X1_0_RCHG_CLK>,
+ <&gcc GCC_PCIE3X1_0_AHB_CLK>,
+ <&gcc GCC_PCIE3X1_0_AUX_CLK>;
+ clock-names = "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng",
+ "ahb",
+ "aux";
+
+ resets = <&gcc GCC_PCIE3X1_0_PIPE_ARES>,
+ <&gcc GCC_PCIE3X1_0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_STICKY_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_M_STICKY_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_M_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_AUX_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_AHB_CLK_ARES>;
+ reset-names = "pipe",
+ "sticky",
+ "axi_s_sticky",
+ "axi_s",
+ "axi_m_sticky",
+ "axi_m",
+ "aux",
+ "ahb";
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ interconnects = <&gcc MASTER_SNOC_PCIE3_1_M &gcc SLAVE_SNOC_PCIE3_1_M>,
+ <&gcc MASTER_ANOC_PCIE3_1_S &gcc SLAVE_ANOC_PCIE3_1_S>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ msi-map = <0x0 &v2m0 0x0 0xffd>;
+ status = "disabled";
+ };
+
+ pcie1: pcie@...00000 {
+ compatible = "qcom,pcie-ipq9574";
+ reg = <0x00088000 0x3000>,
+ <0x18000000 0xf1d>,
+ <0x18000f20 0xa8>,
+ <0x18001000 0x1000>,
+ <0x18100000 0x1000>,
+ <0x0008b000 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0 0x18200000 0x18200000 0 0x00100000>,
+ <0x02000000 0 0x18300000 0x18300000 0 0x07d00000>;
+
+ interrupts = <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 412 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 413 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 414 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 415 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE3X2_AXI_M_CLK>,
+ <&gcc GCC_PCIE3X2_AXI_S_CLK>,
+ <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE3X2_RCHG_CLK>,
+ <&gcc GCC_PCIE3X2_AHB_CLK>,
+ <&gcc GCC_PCIE3X2_AUX_CLK>;
+ clock-names = "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng",
+ "ahb",
+ "aux";
+
+ resets = <&gcc GCC_PCIE3X2_PIPE_ARES>,
+ <&gcc GCC_PCIE3X2_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_S_STICKY_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_S_CLK_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_M_STICKY_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_M_CLK_ARES>,
+ <&gcc GCC_PCIE3X2_AUX_CLK_ARES>,
+ <&gcc GCC_PCIE3X2_AHB_CLK_ARES>;
+ reset-names = "pipe",
+ "sticky",
+ "axi_s_sticky",
+ "axi_s",
+ "axi_m_sticky",
+ "axi_m",
+ "aux",
+ "ahb";
+
+ phys = <&pcie1_phy>;
+ phy-names = "pciephy";
+
+ interconnects = <&gcc MASTER_SNOC_PCIE3_2_M &gcc SLAVE_SNOC_PCIE3_2_M>,
+ <&gcc MASTER_ANOC_PCIE3_2_S &gcc SLAVE_ANOC_PCIE3_2_S>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ msi-map = <0x0 &v2m0 0x0 0xffd>;
+ status = "disabled";
+ };
+
intc: interrupt-controller@...0000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
--
2.34.1
Powered by blists - more mailing lists