linux-kernel - [PATCH v5 0/2] Enable SDHC1 and SDHC2 on QCS615

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Message-Id: <20241217101017.2933587-1-quic_yuanjiey@quicinc.com>
Date: Tue, 17 Dec 2024 18:10:15 +0800
From: Yuanjie Yang <quic_yuanjiey@...cinc.com>
To: ulf.hansson@...aro.org, robh@...nel.org, krzk+dt@...nel.org,
        conor+dt@...nel.org, bhupesh.sharma@...aro.org, andersson@...nel.org,
        konradybcio@...nel.org
Cc: linux-mmc@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        quic_tingweiz@...cinc.com, quic_yuanjiey@...cinc.com
Subject: [PATCH v5 0/2] Enable SDHC1 and SDHC2 on QCS615

Add SDHC1 and SDHC2 support to the QCS615 Ride platform. The
SDHC1 and SDHC2 of QCS615 are derived from SM6115. Include
the configuration of SDHC1-related and SDHC2-related opp,
power, and interconnect settings in the device tree.

Signed-off-by: Yuanjie Yang <quic_yuanjiey@...cinc.com>

---
This patch series depends on below patch series:
- gcc: https://lore.kernel.org/all/20241022-qcs615-clock-driver-v4-0-3d716ad0d987@quicinc.com/

Changes in v5:
- Modify SDHC1 and SDHC2 interconnects, for the cpu path, use
QCOM_ICC_TAG_ACTIVE_ONLY to replace QCOM_ICC_TAG_ALWAYS
- For SDHC1 and SDHC2, Add a newline before status
- Rebase Change on tag: next-20241217
- Modify dependency changes
- Link to v4: https://lore.kernel.org/all/20241206023711.2541716-1-quic_yuanjiey@quicinc.com/

Changes in v4:
- Move properties which are not properties of the SoC to board DTS
- Add ice region to SDHC1 Node reg
- Add 50Mhz 200Mhz to SDHC1 opp table, add 50Mhz to SDHC2 opp table 
- fix SDHC2 Node compatible space
- Link to v3: https://lore.kernel.org/all/20241122065101.1918470-1-quic_yuanjiey@quicinc.com/

Changes in v3:
- Improve the commit messages and cover letter
- Link to v2: https://lore.kernel.org/all/20241106072343.2070933-1-quic_yuanjiey@quicinc.com/

Changes in v2:
- Improve the commit messages and cover letter
- Remove applied patches 1
- Pad sdhc_1 node and sdhc_2 node register addresses to 8 hex digits
- Adjust sdhc_1 node and sdhc_2 node register addresses to hexadecimal
- Modify sdhc_2 vqmmc-supply incorrect power configuration
- Link to v1: https://lore.kernel.org/all/20241023092708.604195-1-quic_yuanjiey@quicinc.com/

---

Yuanjie Yang (2):
  arm64: dts: qcom: qcs615: add SDHC1 and SDHC2
  arm64: dts: qcom: qcs615-ride: enable SDHC1 and SDHC2

 arch/arm64/boot/dts/qcom/qcs615-ride.dts |  37 ++++
 arch/arm64/boot/dts/qcom/qcs615.dtsi     | 211 +++++++++++++++++++++++
 2 files changed, 248 insertions(+)

-- 
2.34.1