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Message-ID: <20241219000400.GF1444967@rocinante>
Date: Thu, 19 Dec 2024 09:04:00 +0900
From: Krzysztof WilczyƄski <kw@...ux.com>
To: Thippeswamy Havalige <thippesw@....com>
Cc: manivannan.sadhasivam@...aro.org, robh@...nel.org, bhelgaas@...gle.com,
	devicetree@...r.kernel.org, conor+dt@...nel.org, krzk+dt@...nel.org,
	bharat.kumar.gogada@....com, michal.simek@....com,
	lpieralisi@...nel.org, linux-pci@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 0/2] Add support for CPM5 controller 1

Hello,

> This patch series introduces support for the second Root Port controller in
> the Xilinx Versal Premium CPM5 block. The Versal Premium platform features
> two Type-A Root Port controllers operating at Gen5 speed. However, the
> error interrupt registers and their corresponding bits are located at
> different offsets for Controller 0 and Controller 1.
> 
> To handle these differences, the series includes:
> 
> A new compatible string for the second Root Port controller in the device
> tree bindings.
> 
> Driver updates to manage platform-specific interrupt registers and offsets
> for both controllers using the new compatible string.

Applied to controller/xilinx-cpm, thank you!

[01/02] dt-bindings: PCI: xilinx-cpm: Add compatible string for CPM5 host1
        https://git.kernel.org/pci/pci/c/5c911b4659d5

[02/02] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port Controller 1
        https://git.kernel.org/pci/pci/c/

	Krzysztof

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