linux-kernel - Re: [PATCH v3] soc: qcom: llcc: Enable LLCC

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Message-ID: <Z2Unnbj_umau4XSR@hovoldconsulting.com>
Date: Fri, 20 Dec 2024 09:15:25 +0100
From: Johan Hovold <johan@...nel.org>
To: Konrad Dybcio <konradybcio@...nel.org>
Cc: Bjorn Andersson <andersson@...nel.org>,
	Sibi Sankar <quic_sibis@...cinc.com>,
	Bryan O'Donoghue <bryan.odonoghue@...aro.org>,
	Rajendra Nayak <quic_rjendra@...cinc.com>,
	Marijn Suijten <marijn.suijten@...ainline.org>,
	linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
	Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
	stable@...r.kernel.org
Subject: Re: [PATCH v3] soc: qcom: llcc: Enable LLCC_WRCACHE at boot on X1

On Thu, Dec 19, 2024 at 07:53:29PM +0100, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> 
> The Last Level Cache is split into many slices, each one of which can
> be toggled on or off.
> 
> Only certain slices are recommended to be turned on unconditionally,
> in order to reach optimal performance/latency/power levels.
> 
> Enable WRCACHE on X1 at boot, in accordance with internal
> recommendations.

Thanks for the update. Can you say something about what WRCACHE is used
for as well?

> No significant performance difference is expected.

This matches my findings (and it seems the slice has not been left
enabled by the boot firmware).

> Fixes: b3cf69a43502 ("soc: qcom: llcc: Add configuration data for X1E80100")
> Cc: stable@...r.kernel.org
> Reviewed-by: Rajendra Nayak <quic_rjendra@...cinc.com>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>

Reviewed-by: Johan Hovold <johan+linaro@...nel.org>
Tested-by: Johan Hovold <johan+linaro@...nel.org>

Johan