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Message-ID: <19fa7f66-ab50-4cd0-8fb7-4f126736ebc3@oss.qualcomm.com>
Date: Fri, 20 Dec 2024 11:16:45 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Ziyue Zhang <quic_ziyuzhan@...cinc.com>, vkoul@...nel.org,
kishon@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, dmitry.baryshkov@...aro.org,
neil.armstrong@...aro.org, abel.vesa@...aro.org,
manivannan.sadhasivam@...aro.org, lpieralisi@...nel.org, kw@...ux.com,
bhelgaas@...gle.com, andersson@...nel.org, konradybcio@...nel.org
Cc: linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-pci@...r.kernel.org, quic_qianyu@...cinc.com,
quic_krichai@...cinc.com, quic_vbadigan@...cinc.com
Subject: Re: [PATCH v3 5/8] arm64: dts: qcom: qcs8300: enable pcie0 for
qcs8300 soc
On 20.12.2024 6:52 AM, Ziyue Zhang wrote:
> Add configurations in devicetree for PCIe0, including registers, clocks,
> interrupts and phy setting sequence.
>
> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Konrad
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