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Message-ID: <20d95d18-ddbc-423e-ab15-d246dc605527@rock-chips.com>
Date: Fri, 20 Dec 2024 09:46:24 +0800
From: Damon Ding <damon.ding@...k-chips.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Cc: heiko@...ech.de, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, rfoss@...nel.org, vkoul@...nel.org,
sebastian.reichel@...labora.com, cristian.ciocaltea@...labora.com,
l.stach@...gutronix.de, andy.yan@...k-chips.com, hjc@...k-chips.com,
algea.cao@...k-chips.com, kever.yang@...k-chips.com,
dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org
Subject: Re: [PATCH v3 04/15] phy: phy-rockchip-samsung-hdptx: Rename some
register names related to DP
Hi Dmitry,
On 2024/12/20 8:22, Dmitry Baryshkov wrote:
> On Thu, Dec 19, 2024 at 04:05:53PM +0800, Damon Ding wrote:
>> The modifications of DP register names are as follows:
>> - Add the '_MASK' suffix to some registers to ensure consistency.
>> - Complete the names of some register to their full names.
>> - Swap the definitions of LCPLL_REF and ROPLL_REF.
>
> Three unrelated changes, ideally means three commits (I won't insist on
> that though). Also please mention that LCPLL_REF and ROPLL_REF were not
> used by the existing driver, so it's not a bug and there is no need to
> backport it.
>
Indeed, it would be better to split this patch into three different
commits. However, I still want to keep the fixes for LCPLL_REF and
ROPLL_REF because, according to the datasheet, they are indeed
incorrect. And I will describe the suggestions you mentioned in the
commit message.
>>
>> Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver")
>> Signed-off-by: Damon Ding <damon.ding@...k-chips.com>
>> ---
>> .../phy/rockchip/phy-rockchip-samsung-hdptx.c | 64 +++++++++----------
>> 1 file changed, 32 insertions(+), 32 deletions(-)
>>
>> diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
>> index ceab9c71d3b5..c1b9c73f5f9f 100644
>> --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
>> +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
>> @@ -69,41 +69,41 @@
>> #define ROPLL_PMS_IQDIV_RSTN BIT(5)
>> /* CMN_REG(005e) */
>> #define ROPLL_SDM_EN_MASK BIT(6)
>> -#define ROPLL_SDM_FRAC_EN_RBR BIT(3)
>> -#define ROPLL_SDM_FRAC_EN_HBR BIT(2)
>> -#define ROPLL_SDM_FRAC_EN_HBR2 BIT(1)
>> -#define ROPLL_SDM_FRAC_EN_HBR3 BIT(0)
>> +#define ROPLL_SDC_FRAC_EN_RBR_MASK BIT(3)
>> +#define ROPLL_SDC_FRAC_EN_HBR_MASK BIT(2)
>> +#define ROPLL_SDC_FRAC_EN_HBR2_MASK BIT(1)
>> +#define ROPLL_SDM_FRAC_EN_HBR3_MASK BIT(0)
>> /* CMN_REG(0064) */
>> #define ROPLL_SDM_NUM_SIGN_RBR_MASK BIT(3)
>> /* CMN_REG(0069) */
>> #define ROPLL_SDC_N_RBR_MASK GENMASK(2, 0)
>> /* CMN_REG(0074) */
>> -#define ROPLL_SDC_NDIV_RSTN BIT(2)
>> -#define ROPLL_SSC_EN BIT(0)
>> +#define ROPLL_SDC_NDIV_RSTN_MASK BIT(2)
>> +#define ROPLL_SSC_EN_MASK BIT(0)
>> /* CMN_REG(0081) */
>> -#define OVRD_PLL_CD_CLK_EN BIT(8)
>> -#define PLL_CD_HSCLK_EAST_EN BIT(0)
>> +#define OVRD_PLL_CD_CLK_EN_MASK BIT(8)
>> +#define ANA_PLL_CD_HSCLK_EAST_EN_MASK BIT(0)
>> /* CMN_REG(0086) */
>> #define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4)
>> #define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1)
> > #define PLL_PCG_CLK_EN BIT(0)
>> /* CMN_REG(0087) */
>> -#define PLL_FRL_MODE_EN BIT(3)
>> -#define PLL_TX_HS_CLK_EN BIT(2)
>> +#define ANA_PLL_FRL_MODE_EN_MASK BIT(3)
>> +#define ANA_PLL_TX_HS_CLK_EN_MASK BIT(2)
>> /* CMN_REG(0089) */
>> #define LCPLL_ALONE_MODE BIT(1)
>> /* CMN_REG(0097) */
>> -#define DIG_CLK_SEL BIT(1)
>> -#define ROPLL_REF BIT(1)
>> -#define LCPLL_REF 0
>> +#define DIG_CLK_SEL_MASK BIT(1)
>> +#define LCPLL_REF BIT(1)
>> +#define ROPLL_REF 0
>> /* CMN_REG(0099) */
>> #define CMN_ROPLL_ALONE_MODE BIT(2)
>> #define ROPLL_ALONE_MODE BIT(2)
>> /* CMN_REG(009a) */
>> -#define HS_SPEED_SEL BIT(0)
>> +#define HS_SPEED_SEL_MASK BIT(0)
>> #define DIV_10_CLOCK BIT(0)
>> /* CMN_REG(009b) */
>> -#define IS_SPEED_SEL BIT(4)
>> +#define LS_SPEED_SEL_MASK BIT(4)
>> #define LINK_SYMBOL_CLOCK BIT(4)
>> #define LINK_SYMBOL_CLOCK1_2 0
>>
>> @@ -165,32 +165,32 @@
>> #define HDMI_MODE BIT(2)
>> #define HDMI_TMDS_FRL_SEL BIT(1)
>> /* LNTOP_REG(0206) */
>> -#define DATA_BUS_SEL BIT(0)
>> +#define DATA_BUS_WIDTH_SEL_MASK BIT(0)
>> #define DATA_BUS_36_40 BIT(0)
>> /* LNTOP_REG(0207) */
>> #define LANE_EN 0xf
>> #define ALL_LANE_EN 0xf
>>
>> /* LANE_REG(0312) */
>> -#define LN0_TX_SER_RATE_SEL_RBR BIT(5)
>> -#define LN0_TX_SER_RATE_SEL_HBR BIT(4)
>> -#define LN0_TX_SER_RATE_SEL_HBR2 BIT(3)
>> -#define LN0_TX_SER_RATE_SEL_HBR3 BIT(2)
>> +#define LN0_TX_SER_RATE_SEL_RBR_MASK BIT(5)
>> +#define LN0_TX_SER_RATE_SEL_HBR_MASK BIT(4)
>> +#define LN0_TX_SER_RATE_SEL_HBR2_MASK BIT(3)
>> +#define LN0_TX_SER_RATE_SEL_HBR3_MASK BIT(2)
>> /* LANE_REG(0412) */
>> -#define LN1_TX_SER_RATE_SEL_RBR BIT(5)
>> -#define LN1_TX_SER_RATE_SEL_HBR BIT(4)
>> -#define LN1_TX_SER_RATE_SEL_HBR2 BIT(3)
>> -#define LN1_TX_SER_RATE_SEL_HBR3 BIT(2)
>> +#define LN1_TX_SER_RATE_SEL_RBR_MASK BIT(5)
>> +#define LN1_TX_SER_RATE_SEL_HBR_MASK BIT(4)
>> +#define LN1_TX_SER_RATE_SEL_HBR2_MASK BIT(3)
>> +#define LN1_TX_SER_RATE_SEL_HBR3_MASK BIT(2)
>> /* LANE_REG(0512) */
>> -#define LN2_TX_SER_RATE_SEL_RBR BIT(5)
>> -#define LN2_TX_SER_RATE_SEL_HBR BIT(4)
>> -#define LN2_TX_SER_RATE_SEL_HBR2 BIT(3)
>> -#define LN2_TX_SER_RATE_SEL_HBR3 BIT(2)
>> +#define LN2_TX_SER_RATE_SEL_RBR_MASK BIT(5)
>> +#define LN2_TX_SER_RATE_SEL_HBR_MASK BIT(4)
>> +#define LN2_TX_SER_RATE_SEL_HBR2_MASK BIT(3)
>> +#define LN2_TX_SER_RATE_SEL_HBR3_MASK BIT(2)
>> /* LANE_REG(0612) */
>> -#define LN3_TX_SER_RATE_SEL_RBR BIT(5)
>> -#define LN3_TX_SER_RATE_SEL_HBR BIT(4)
>> -#define LN3_TX_SER_RATE_SEL_HBR2 BIT(3)
>> -#define LN3_TX_SER_RATE_SEL_HBR3 BIT(2)
>> +#define LN3_TX_SER_RATE_SEL_RBR_MASK BIT(5)
>> +#define LN3_TX_SER_RATE_SEL_HBR_MASK BIT(4)
>> +#define LN3_TX_SER_RATE_SEL_HBR2_MASK BIT(3)
>> +#define LN3_TX_SER_RATE_SEL_HBR3_MASK BIT(2)
>>
>> #define HDMI20_MAX_RATE 600000000
>>
>> --
>> 2.34.1
>>
>
Best regards,
Damon
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