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Message-Id: <20241221-topic-x1p4_soc-v1-2-55347831d73c@oss.qualcomm.com>
Date: Sat, 21 Dec 2024 13:36:01 +0100
From: Konrad Dybcio <konradybcio@...nel.org>
To: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: Marijn Suijten <marijn.suijten@...ainline.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: [PATCH 2/4] dt-bindings: arm: qcom: Add X1P42100 SoC & CRD
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
The X1 family is split into two parts: the 10- and 12-core parts are
variants of the same silicon with different fusing, whereas the 8-core
ones are a separate design. Thankfully, the software interface is only
barely different, letting us reuse much of the existing X1 work.
Add X1P42100 SoC (and the CRD based on it) as a representative of the
8-core series.
Signed-off-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index d394dffe3fba5a396b85a6093f34e9ef62b6f9cc..c5b7268cd9407c1e8a33b291d541d33c1e5cb6eb 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -99,6 +99,7 @@ description: |
sm8650
x1e78100
x1e80100
+ x1p42100
There are many devices in the list below that run the standard ChromeOS
bootloader setup and use the open source depthcharge bootloader to boot the
@@ -1122,6 +1123,11 @@ properties:
- qcom,x1e80100-qcp
- const: qcom,x1e80100
+ - items:
+ - enum:
+ - qcom,x1p42100-crd
+ - const: qcom,x1p42100
+
# Board compatibles go above
qcom,msm-id:
--
2.47.1
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