linux-kernel - Re: [PATCH v2 0/6] Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300

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Message-ID: <CACRpkdYrmZBC+wm62brjPtArFhxcnNY2=sw+8jHiyproh-kPtQ@mail.gmail.com>
Date: Sun, 22 Dec 2024 09:53:25 +0100
From: Linus Walleij <linus.walleij@...aro.org>
To: Lijuan Gao <quic_lijuang@...cinc.com>
Cc: Bjorn Andersson <andersson@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Jingyi Wang <quic_jingyw@...cinc.com>, Konrad Dybcio <konradybcio@...nel.org>, kernel@...cinc.com, 
	linux-arm-msm@...r.kernel.org, linux-gpio@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: Re: [PATCH v2 0/6] Correct the number of GPIOs in gpio-ranges for
 QCS615 and QCS8300

Hi Lijuan,

thanks for your patches!

On Thu, Dec 19, 2024 at 9:00 AM Lijuan Gao <quic_lijuang@...cinc.com> wrote:

> The UFS_RESET pin on Qualcomm SoCs are controlled by TLMM and exposed
> through the GPIO framework. It is expected to be wired to the reset pin
> of the primary UFS memory so that the UFS driver can toggle it.
>
> The UFS_RESET pin is exported as GPIOs in addtion to the real GPIOs. The
> QCS615 TLMM pin controller has GPIOs 0-122, so correct the gpio-rangs to
> 124. The QCS8300 TLMM pin controller has GPIOs 0-132, so correct the
> gpio-rangs to 134.
(...)
> Lijuan Gao (6):
>       dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615
>       dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300
>       pinctrl: qcom: correct the ngpios entry for QCS615
>       pinctrl: qcom: correct the ngpios entry for QCS8300

I'm planning to apply these 4 after v3 arrives with the collected ACKs etc.

Yours,
Linus Walleij