linux-kernel - Re: [PATCH 09/10] x86/mm: enable AMD translation cache extensions

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Message-ID: <20241222113811.GY11133@noisy.programming.kicks-ass.net>
Date: Sun, 22 Dec 2024 12:38:11 +0100
From: Peter Zijlstra <peterz@...radead.org>
To: Rik van Riel <riel@...riel.com>
Cc: x86@...nel.org, linux-kernel@...r.kernel.org, kernel-team@...a.com,
	dave.hansen@...ux.intel.com, luto@...nel.org, tglx@...utronix.de,
	mingo@...hat.com, bp@...en8.de, hpa@...or.com,
	akpm@...ux-foundation.org
Subject: Re: [PATCH 09/10] x86/mm: enable AMD translation cache extensions

On Sat, Dec 21, 2024 at 11:06:41PM -0500, Rik van Riel wrote:
> With AMD TCE (translation cache extensions) only the intermediate mappings

Only the leave mapings, as written this all don't make sense,

> that cover the address range zapped by INVLPG / INVLPGB get invalidated,
> rather than all intermediate mappings getting zapped at every TLB invalidation.
> 
> This can help reduce the TLB miss rate, by keeping more intermediate
> mappings in the cache.