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Message-ID: <20241222175314.151437-2-towinchenmi@gmail.com>
Date: Mon, 23 Dec 2024 01:52:01 +0800
From: Nick Chan <towinchenmi@...il.com>
To: Hector Martin <marcan@...can.st>,
Sven Peter <sven@...npeter.dev>,
Alyssa Rosenzweig <alyssa@...enzweig.io>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
asahi@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: Nick Chan <towinchenmi@...il.com>
Subject: [PATCH 1/9] arm64: dts: apple: s5l8960x: Add cpufreq nodes
Add cpufreq nodes for Apple A7 SoC.
Signed-off-by: Nick Chan <towinchenmi@...il.com>
---
arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi | 1 +
arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi | 1 +
arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi | 1 +
arch/arm64/boot/dts/apple/s5l8960x-opp.dtsi | 45 +++++++++++++++++++
arch/arm64/boot/dts/apple/s5l8960x.dtsi | 10 +++++
arch/arm64/boot/dts/apple/s5l8965x-opp.dtsi | 45 +++++++++++++++++++
6 files changed, 103 insertions(+)
create mode 100644 arch/arm64/boot/dts/apple/s5l8960x-opp.dtsi
create mode 100644 arch/arm64/boot/dts/apple/s5l8965x-opp.dtsi
diff --git a/arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi b/arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi
index 0b16adf07f79..83c0a4deb5ba 100644
--- a/arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi
+++ b/arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi
@@ -8,6 +8,7 @@
#include "s5l8960x.dtsi"
#include "s5l8960x-common.dtsi"
+#include "s5l8960x-opp.dtsi"
#include <dt-bindings/input/input.h>
/ {
diff --git a/arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi b/arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi
index 741c5a9f21dd..d88894e0fce7 100644
--- a/arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi
+++ b/arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi
@@ -8,6 +8,7 @@
#include "s5l8960x.dtsi"
#include "s5l8960x-common.dtsi"
+#include "s5l8965x-opp.dtsi"
#include <dt-bindings/input/input.h>
/ {
diff --git a/arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi b/arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi
index b27ef5680626..261b5008a6b4 100644
--- a/arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi
+++ b/arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi
@@ -8,6 +8,7 @@
#include "s5l8960x.dtsi"
#include "s5l8960x-common.dtsi"
+#include "s5l8960x-opp.dtsi"
#include <dt-bindings/input/input.h>
/ {
diff --git a/arch/arm64/boot/dts/apple/s5l8960x-opp.dtsi b/arch/arm64/boot/dts/apple/s5l8960x-opp.dtsi
new file mode 100644
index 000000000000..e4d568c4a119
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/s5l8960x-opp.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Operating points for Apple S5L8960X "A7" SoC, Up to 1296 MHz
+ *
+ * target-type: N51, N53, J85, J86. J87, J85m, J86m, J87m
+ *
+ * Copyright (c) 2024, Nick Chan <towinchenmi@...il.com>
+ */
+
+/ {
+ cyclone_opp: opp-table {
+ compatible = "operating-points-v2";
+
+ opp01 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-level = <1>;
+ clock-latency-ns = <15500>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <396000000>;
+ opp-level = <2>;
+ clock-latency-ns = <43000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-level = <3>;
+ clock-latency-ns = <26000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <840000000>;
+ opp-level = <4>;
+ clock-latency-ns = <30000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1128000000>;
+ opp-level = <5>;
+ clock-latency-ns = <39500>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-level = <6>;
+ clock-latency-ns = <45500>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/apple/s5l8960x.dtsi b/arch/arm64/boot/dts/apple/s5l8960x.dtsi
index 0218ecac1d83..449c69d0d92f 100644
--- a/arch/arm64/boot/dts/apple/s5l8960x.dtsi
+++ b/arch/arm64/boot/dts/apple/s5l8960x.dtsi
@@ -33,6 +33,8 @@ cpu0: cpu@0 {
compatible = "apple,cyclone";
reg = <0x0 0x0>;
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&cyclone_opp>;
+ performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
};
@@ -41,6 +43,8 @@ cpu1: cpu@1 {
compatible = "apple,cyclone";
reg = <0x0 0x1>;
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&cyclone_opp>;
+ performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
};
@@ -53,6 +57,12 @@ soc {
nonposted-mmio;
ranges;
+ cpufreq: performance-controller@...220000 {
+ compatible = "apple,s5l8960x-cluster-cpufreq";
+ reg = <0x2 0x02220000 0 0x1000>;
+ #performance-domain-cells = <0>;
+ };
+
serial0: serial@...0a0000 {
compatible = "apple,s5l-uart";
reg = <0x2 0x0a0a0000 0x0 0x4000>;
diff --git a/arch/arm64/boot/dts/apple/s5l8965x-opp.dtsi b/arch/arm64/boot/dts/apple/s5l8965x-opp.dtsi
new file mode 100644
index 000000000000..d34dae74a90c
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/s5l8965x-opp.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Operating points for Apple S5L8965X "A7" Rev A SoC, Up to 1392 MHz
+ *
+ * target-type: J71, J72, J73
+ *
+ * Copyright (c) 2024, Nick Chan <towinchenmi@...il.com>
+ */
+
+/ {
+ cyclone_opp: opp-table {
+ compatible = "operating-points-v2";
+
+ opp01 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-level = <1>;
+ clock-latency-ns = <10000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-level = <2>;
+ clock-latency-ns = <49000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <840000000>;
+ opp-level = <3>;
+ clock-latency-ns = <30000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1128000000>;
+ opp-level = <4>;
+ clock-latency-ns = <39500>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-level = <5>;
+ clock-latency-ns = <45500>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1392000000>;
+ opp-level = <6>;
+ clock-latency-ns = <46500>;
+ };
+ };
+};
--
2.47.1
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