linux-kernel - Re: [PATCH v3 1/6] dt-bindings: PCI: Add binding for qps615

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <eysqoiiizunkjxqyvfaxbx4szwnz4osv42j7xr247irnthifwu@nhxytsl4brvu>
Date: Tue, 24 Dec 2024 11:49:42 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>
Cc: Bjorn Helgaas <helgaas@...nel.org>, andersson@...nel.org, 
	Bjorn Helgaas <bhelgaas@...gle.com>, Lorenzo Pieralisi <lpieralisi@...nel.org>, 
	Krzysztof Wilczyński <kw@...ux.com>, Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
	Conor Dooley <conor+dt@...nel.org>, Konrad Dybcio <konradybcio@...nel.org>, 
	cros-qcom-dts-watchers@...omium.org, Jingoo Han <jingoohan1@...il.com>, 
	Bartosz Golaszewski <brgl@...ev.pl>, quic_vbadigan@...cinc.com, linux-arm-msm@...r.kernel.org, 
	linux-pci@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 1/6] dt-bindings: PCI: Add binding for qps615

On Tue, Dec 24, 2024 at 02:41:10PM +0530, Krishna Chaitanya Chundru wrote:
> 
> 
> On 12/5/2024 2:55 AM, Bjorn Helgaas wrote:
> > On Tue, Nov 12, 2024 at 08:31:33PM +0530, Krishna chaitanya chundru wrote:
> > > Add binding describing the Qualcomm PCIe switch, QPS615,
> > > which provides Ethernet MAC integrated to the 3rd downstream port
> > > and two downstream PCIe ports.
> > 
> > > +$defs:
> > > +  qps615-node:
> > > +    type: object
> > > +
> > > +    properties:
> > > +      qcom,l0s-entry-delay-ns:
> > > +        description: Aspm l0s entry delay.
> > > +
> > > +      qcom,l1-entry-delay-ns:
> > > +        description: Aspm l1 entry delay.
> > 
> > To match spec usage:
> > s/Aspm/ASPM/
> > s/l0s/L0s/
> > s/l1/L1/
> > 
> > Other than the fact that qps615 needs the driver to configure these,
> > there's nothing qcom-specific here, so I suggest the names should omit
> > "qcom" and include "aspm".
> > 
> > > +    pcie {
> > > +        #address-cells = <3>;
> > > +        #size-cells = <2>;
> > > +
> > > +        pcie@0 {
> > > +            device_type = "pci";
> > > +            reg = <0x0 0x0 0x0 0x0 0x0>;
> > > +
> > > +            #address-cells = <3>;
> > > +            #size-cells = <2>;
> > > +            ranges;
> > > +            bus-range = <0x01 0xff>;
> > > +
> > > +            pcie@0,0 {
> > > +                compatible = "pci1179,0623";
> > > +                reg = <0x10000 0x0 0x0 0x0 0x0>;
> > > +                device_type = "pci";
> > > +                #address-cells = <3>;
> > > +                #size-cells = <2>;
> > > +                ranges;
> > > +                bus-range = <0x02 0xff>;
> > 
> > This binding describes a switch.  I don't think bus-range should
> > appear here at all because it is not a feature of the hardware (unless
> > the switch ports are broken and their Secondary/Subordinate Bus
> > Numbers are hard-wired).
> > 
> > The Primary/Secondary/Subordinate Bus Numbers of all switch ports
> > should be writable and the PCI core knows how to manage them.
> > 
> Bjorn,
> 
> The dt binding check is throwing an error if we don't keep bus-range
> property for that reason we added it, from dt binding perspective i think it
> is mandatory to add this property.

Could you please provide an error message? I don't see any of the PCIe
bindingins declaring bus-range as mandatory. I might be missing it
though.

> 
> - Krishna Chaitanya.
> > Bjorn

-- 
With best wishes
Dmitry