[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <7sy7ogdlvvahk7pdfusdi4sx5fc2qoqexvgcwskoxywnmtx6tt@2od6sbwzohg3>
Date: Tue, 24 Dec 2024 15:25:38 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Pratyush Brahma <quic_pbrahma@...cinc.com>
Cc: andersson@...nel.org, konradybcio@...nel.org, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/1] arm64: dts: qcom: qcs8300: Add device node for
gfx_smmu
On Tue, Dec 24, 2024 at 03:35:21PM +0530, Pratyush Brahma wrote:
> Adding device node for gfx smmu that is served for gpu.
>
> This patch depends on the patch series [1] posted by Imran Shaik
> adding the clock support for gpu.
>
> [1] https://lore.kernel.org/all/802d32f1-ff7e-4d61-83f1-f804ee1750ed@oss.qualcomm.com/
>
> Signed-off-by: Pratyush Brahma <quic_pbrahma@...cinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 37 +++++++++++++++++++++++++++
> 1 file changed, 37 insertions(+)
It doesn't seem that this was tested against the current bindings.
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> index 80226992a65d..8eb688e2df0a 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> @@ -816,6 +816,43 @@
> #power-domain-cells = <1>;
> };
>
> + adreno_smmu: iommu@...0000 {
> + compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu",
> + "qcom,smmu-500", "arm,mmu-500";
> + reg = <0x0 0x3da0000 0x0 0x20000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <2>;
> + dma-coherent;
> +
> + power-domains = <&gpucc GPU_CC_CX_GDSC>;
> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
> + <&gpucc GPU_CC_AHB_CLK>,
> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
> + <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> + <&gpucc GPU_CC_HUB_AON_CLK>;
> + clock-names = "gcc_gpu_memnoc_gfx_clk",
> + "gcc_gpu_snoc_dvm_gfx_clk",
> + "gpu_cc_ahb_clk",
> + "gpu_cc_hlos1_vote_gpu_smmu_clk",
> + "gpu_cc_cx_gmu_clk",
> + "gpu_cc_hub_cx_int_clk",
> + "gpu_cc_hub_aon_clk";
> + interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> pmu@...1000 {
> compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
> reg = <0x0 0x9091000 0x0 0x1000>;
> --
> 2.17.1
>
--
With best wishes
Dmitry
Powered by blists - more mailing lists