linux-kernel - [PATCH v2 17/27] spi: zynqmp-gqspi: Support per spi-mem operation frequency switches

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Message-Id: <20241224-winbond-6-11-rc1-quad-support-v2-17-ad218dbc406f@bootlin.com>
Date: Tue, 24 Dec 2024 18:06:02 +0100
From: Miquel Raynal <miquel.raynal@...tlin.com>
To: Mark Brown <broonie@...nel.org>, Sanjay R Mehta <sanju.mehta@....com>, 
 Serge Semin <fancer.lancer@...il.com>, Han Xu <han.xu@....com>, 
 Conor Dooley <conor.dooley@...rochip.com>, 
 Daire McNamara <daire.mcnamara@...rochip.com>, 
 Matthias Brugger <matthias.bgg@...il.com>, 
 AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>, 
 Haibo Chen <haibo.chen@....com>, Yogesh Gaur <yogeshgaur.83@...il.com>, 
 Heiko Stuebner <heiko@...ech.de>, Michal Simek <michal.simek@....com>, 
 Miquel Raynal <miquel.raynal@...tlin.com>, 
 Richard Weinberger <richard@....at>, Vignesh Raghavendra <vigneshr@...com>, 
 Jacky Huang <ychuang3@...oton.com>, Shan-Chun Hung <schung@...oton.com>, 
 Chin-Ting Kuo <chin-ting_kuo@...eedtech.com>, 
 Cédric Le Goater <clg@...d.org>, 
 Joel Stanley <joel@....id.au>, Andrew Jeffery <andrew@...econstruct.com.au>, 
 Avi Fishman <avifishman70@...il.com>, Tomer Maimon <tmaimon77@...il.com>, 
 Tali Perry <tali.perry1@...il.com>, Patrick Venture <venture@...gle.com>, 
 Nancy Yuen <yuenn@...gle.com>, Benjamin Fair <benjaminfair@...gle.com>, 
 Maxime Coquelin <mcoquelin.stm32@...il.com>, 
 Alexandre Torgue <alexandre.torgue@...s.st.com>, 
 Raju Rangoju <Raju.Rangoju@....com>
Cc: Thomas Petazzoni <thomas.petazzoni@...tlin.com>, 
 Steam Lin <stlin2@...bond.com>, linux-spi@...r.kernel.org, 
 linux-kernel@...r.kernel.org, imx@...ts.linux.dev, 
 linux-riscv@...ts.infradead.org, linux-arm-kernel@...ts.infradead.org, 
 linux-mediatek@...ts.infradead.org, linux-rockchip@...ts.infradead.org, 
 linux-mtd@...ts.infradead.org, linux-aspeed@...ts.ozlabs.org, 
 openbmc@...ts.ozlabs.org, linux-stm32@...md-mailman.stormreply.com
Subject: [PATCH v2 17/27] spi: zynqmp-gqspi: Support per spi-mem operation
 frequency switches

Every ->exec_op() call correctly configures the spi bus speed to the
maximum allowed frequency for the memory using the constant spi default
parameter. Since we can now have per-operation constraints, let's use
the value that comes from the spi-mem operation structure instead. In
case there is no specific limitation for this operation, the default spi
device value will be given anyway.

The per-operation frequency capability is thus advertised to the spi-mem
core.

Cc: Michal Simek <michal.simek@....com>
Signed-off-by: Miquel Raynal <miquel.raynal@...tlin.com>
---
 drivers/spi/spi-zynqmp-gqspi.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c
index 549a6e0c96546211223dd45e8e70620fa5fd18ab..d800d79f62a70c74551e1ad6f628685ec6c18b0d 100644
--- a/drivers/spi/spi-zynqmp-gqspi.c
+++ b/drivers/spi/spi-zynqmp-gqspi.c
@@ -535,7 +535,7 @@ static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
  * zynqmp_qspi_config_op - Configure QSPI controller for specified
  *				transfer
  * @xqspi:	Pointer to the zynqmp_qspi structure
- * @qspi:	Pointer to the spi_device structure
+ * @op:		The memory operation to execute
  *
  * Sets the operational mode of QSPI controller for the next QSPI transfer and
  * sets the requested clock frequency.
@@ -553,12 +553,12 @@ static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
  *	frequency supported by controller.
  */
 static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi,
-				 struct spi_device *qspi)
+				 const struct spi_mem_op *op)
 {
 	ulong clk_rate;
 	u32 config_reg, req_speed_hz, baud_rate_val = 0;
 
-	req_speed_hz = qspi->max_speed_hz;
+	req_speed_hz = op->max_freq;
 
 	if (xqspi->speed_hz != req_speed_hz) {
 		xqspi->speed_hz = req_speed_hz;
@@ -1072,7 +1072,7 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem,
 		op->dummy.buswidth, op->data.buswidth);
 
 	mutex_lock(&xqspi->op_lock);
-	zynqmp_qspi_config_op(xqspi, mem->spi);
+	zynqmp_qspi_config_op(xqspi, op);
 	zynqmp_qspi_chipselect(mem->spi, false);
 	genfifoentry |= xqspi->genfifocs;
 	genfifoentry |= xqspi->genfifobus;
@@ -1224,6 +1224,10 @@ static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
 	.exec_op = zynqmp_qspi_exec_op,
 };
 
+static const struct spi_controller_mem_caps zynqmp_qspi_mem_caps = {
+	.per_op_freq = true,
+};
+
 /**
  * zynqmp_qspi_probe - Probe method for the QSPI driver
  * @pdev:	Pointer to the platform_device structure
@@ -1333,6 +1337,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
 
 	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
 	ctlr->mem_ops = &zynqmp_qspi_mem_ops;
+	ctlr->mem_caps = &zynqmp_qspi_mem_caps;
 	ctlr->setup = zynqmp_qspi_setup_op;
 	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
 	ctlr->dev.of_node = np;

-- 
2.47.0