linux-kernel - Re: [PATCH v4 12/15] cxl/pci: Add error handler for CXL PCIe Port RAS errors

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Message-ID: <20241224184349.0000424b@huawei.com>
Date: Tue, 24 Dec 2024 18:43:49 +0000
From: Jonathan Cameron <Jonathan.Cameron@...wei.com>
To: Terry Bowman <terry.bowman@....com>
CC: <linux-cxl@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linux-pci@...r.kernel.org>, <nifan.cxl@...il.com>, <ming4.li@...el.com>,
	<dave@...olabs.net>, <dave.jiang@...el.com>, <alison.schofield@...el.com>,
	<vishal.l.verma@...el.com>, <dan.j.williams@...el.com>,
	<bhelgaas@...gle.com>, <mahesh@...ux.ibm.com>, <ira.weiny@...el.com>,
	<oohall@...il.com>, <Benjamin.Cheatham@....com>, <rrichter@....com>,
	<nathan.fontenot@....com>, <Smita.KoralahalliChannabasappa@....com>,
	<lukas@...ner.de>, <PradeepVineshReddy.Kodamati@....com>
Subject: Re: [PATCH v4 12/15] cxl/pci: Add error handler for CXL PCIe Port
 RAS errors

On Wed, 11 Dec 2024 17:39:59 -0600
Terry Bowman <terry.bowman@....com> wrote:

> Introduce correctable and uncorrectable CXL PCIe port protocol error
> handlers.
> 
> The handlers will be called with a 'struct pci_dev' parameter
> indicating the CXL Port device requiring handling. The CXL PCIe Port
> device's underlying 'struct device' will match the Port device in the
> CXL topology.
> 
> Use the PCIe Port's device object to find the matching Upstream Switch
> Port, Downstream Switch Port, or Root Port in the CXL topology. The
> matching device will contain a reference to the RAS register block used to
> handle and log the error.
> 
> Invoke the existing __cxl_handle_ras() or __cxl_handle_cor_ras() passing
> a reference to the RAS registers as a parameter. These functions will use
> the register reference to clear the device's RAS status.
> 
> Future patches will assign the error handlers and add trace logging.
> 
> Signed-off-by: Terry Bowman <terry.bowman@....com>
Other than Li Ming's question, LGTM
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>