linux-kernel - Re: [PATCH v7 7/7] iio: accel: adxl345: complete the list of defines

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Message-ID: <CAFXKEHbHEGFPKp7nbFA2u28a5n0aA+0SFaKR0-3ys81FP9pMAA@mail.gmail.com>
Date: Wed, 25 Dec 2024 17:59:07 +0100
From: Lothar Rubusch <l.rubusch@...il.com>
To: Jonathan Cameron <jic23@...nel.org>
Cc: lars@...afoo.de, Michael.Hennerich@...log.com, robh@...nel.org, 
	krzk+dt@...nel.org, conor+dt@...nel.org, devicetree@...r.kernel.org, 
	linux-iio@...r.kernel.org, linux-kernel@...r.kernel.org, eraretuya@...il.com
Subject: Re: [PATCH v7 7/7] iio: accel: adxl345: complete the list of defines

On Sat, Dec 14, 2024 at 1:39 PM Jonathan Cameron <jic23@...nel.org> wrote:
>
> On Fri, 13 Dec 2024 21:19:09 +0000
> Lothar Rubusch <l.rubusch@...il.com> wrote:
>
> > Having interrupts events and FIFO available allows to evaluate the
> > sensor events. Cover the list of interrupt based sensor events. Keep
> > them in the header file for readability.
>
> That makes sense for now, but longer term I'd attempt to restrict the scope
> of these by moving them to the top of core.c
>
> The two bus drivers don't use any of them that I can immediately spot
> and if they do it is likely to be very few.
>
> That may be a good first patch for your next series.

I understand. Actually in v1 of the series I had a patch to move the
defines into _core.c. There were bigger issues, though. Thank you so
much for all the feedback the improvements are impressive to me.

Best,
L

>
> Jonathan
>
>
> >
> > Signed-off-by: Lothar Rubusch <l.rubusch@...il.com>
> > ---
> >  drivers/iio/accel/adxl345.h | 57 +++++++++++++++++++++++++++++++++----
> >  1 file changed, 51 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/iio/accel/adxl345.h b/drivers/iio/accel/adxl345.h
> > index bf9e86cff..df3977bda 100644
> > --- a/drivers/iio/accel/adxl345.h
> > +++ b/drivers/iio/accel/adxl345.h
> > @@ -9,10 +9,35 @@
> >  #define _ADXL345_H_
> >
> >  #define ADXL345_REG_DEVID            0x00
> > +#define ADXL345_REG_THRESH_TAP               0x1D
> >  #define ADXL345_REG_OFSX             0x1E
> >  #define ADXL345_REG_OFSY             0x1F
> >  #define ADXL345_REG_OFSZ             0x20
> >  #define ADXL345_REG_OFS_AXIS(index)  (ADXL345_REG_OFSX + (index))
> > +
> > +/* Tap duration */
> > +#define ADXL345_REG_DUR              0x21
> > +/* Tap latency */
> > +#define ADXL345_REG_LATENT           0x22
> > +/* Tap window */
> > +#define ADXL345_REG_WINDOW           0x23
> > +/* Activity threshold */
> > +#define ADXL345_REG_THRESH_ACT               0x24
> > +/* Inactivity threshold */
> > +#define ADXL345_REG_THRESH_INACT     0x25
> > +/* Inactivity time */
> > +#define ADXL345_REG_TIME_INACT               0x26
> > +/* Axis enable control for activity and inactivity detection */
> > +#define ADXL345_REG_ACT_INACT_CTRL   0x27
> > +/* Free-fall threshold */
> > +#define ADXL345_REG_THRESH_FF                0x28
> > +/* Free-fall time */
> > +#define ADXL345_REG_TIME_FF          0x29
> > +/* Axis control for single tap or double tap */
> > +#define ADXL345_REG_TAP_AXIS         0x2A
> > +/* Source of single tap or double tap */
> > +#define ADXL345_REG_ACT_TAP_STATUS   0x2B
> > +/* Data rate and power mode control */
> >  #define ADXL345_REG_BW_RATE          0x2C
> >  #define ADXL345_REG_POWER_CTL                0x2D
> >  #define ADXL345_REG_INT_ENABLE               0x2E
> > @@ -34,20 +59,40 @@
> >  #define ADXL345_FIFO_CTL_MODE(x)     FIELD_PREP(GENMASK(7, 6), x)
> >
> >  #define ADXL345_INT_DATA_READY               BIT(7)
> > +#define ADXL345_INT_SINGLE_TAP               BIT(6)
> > +#define ADXL345_INT_DOUBLE_TAP               BIT(5)
> > +#define ADXL345_INT_ACTIVITY         BIT(4)
> > +#define ADXL345_INT_INACTIVITY               BIT(3)
> > +#define ADXL345_INT_FREE_FALL                BIT(2)
> >  #define ADXL345_INT_WATERMARK                BIT(1)
> >  #define ADXL345_INT_OVERRUN          BIT(0)
> > +
> > +#define ADXL345_S_TAP_MSK    ADXL345_INT_SINGLE_TAP
> > +#define ADXL345_D_TAP_MSK    ADXL345_INT_DOUBLE_TAP
> > +
> > +/*
> > + * BW_RATE bits - Bandwidth and output data rate. The default value is
> > + * 0x0A, which translates to a 100 Hz output data rate
> > + */
> >  #define ADXL345_BW_RATE                      GENMASK(3, 0)
> > +#define ADXL345_BW_LOW_POWER         BIT(4)
> >  #define ADXL345_BASE_RATE_NANO_HZ    97656250LL
> >
> >  #define ADXL345_POWER_CTL_STANDBY    0x00
> > +#define ADXL345_POWER_CTL_WAKEUP     GENMASK(1, 0)
> > +#define ADXL345_POWER_CTL_SLEEP      BIT(2)
> >  #define ADXL345_POWER_CTL_MEASURE    BIT(3)
> > +#define ADXL345_POWER_CTL_AUTO_SLEEP BIT(4)
> > +#define ADXL345_POWER_CTL_LINK               BIT(5)
> >
> > -#define ADXL345_DATA_FORMAT_RANGE    GENMASK(1, 0)   /* Set the g range */
> > -#define ADXL345_DATA_FORMAT_JUSTIFY  BIT(2)  /* Left-justified (MSB) mode */
> > -#define ADXL345_DATA_FORMAT_FULL_RES BIT(3)  /* Up to 13-bits resolution */
> > -#define ADXL345_DATA_FORMAT_SPI_3WIRE        BIT(6)  /* 3-wire SPI mode */
> > -#define ADXL345_DATA_FORMAT_SELF_TEST        BIT(7)  /* Enable a self test */
> > -
> > +/* Set the g range */
> > +#define ADXL345_DATA_FORMAT_RANGE    GENMASK(1, 0)
> > +/* Data is left justified */
> > +#define ADXL345_DATA_FORMAT_JUSTIFY  BIT(2)
> > +/* Up to 13-bits resolution */
> > +#define ADXL345_DATA_FORMAT_FULL_RES BIT(3)
> > +#define ADXL345_DATA_FORMAT_SPI_3WIRE        BIT(6)
> > +#define ADXL345_DATA_FORMAT_SELF_TEST        BIT(7)
> >  #define ADXL345_DATA_FORMAT_2G               0
> >  #define ADXL345_DATA_FORMAT_4G               1
> >  #define ADXL345_DATA_FORMAT_8G               2
>