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Message-Id: <20241226063313.3267515-5-damon.ding@rock-chips.com> Date: Thu, 26 Dec 2024 14:33:00 +0800 From: Damon Ding <damon.ding@...k-chips.com> To: heiko@...ech.de Cc: robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org, rfoss@...nel.org, vkoul@...nel.org, sebastian.reichel@...labora.com, cristian.ciocaltea@...labora.com, l.stach@...gutronix.de, andy.yan@...k-chips.com, hjc@...k-chips.com, algea.cao@...k-chips.com, kever.yang@...k-chips.com, dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org, Damon Ding <damon.ding@...k-chips.com> Subject: [PATCH v4 04/17] phy: phy-rockchip-samsung-hdptx: Swap the definitions of LCPLL_REF and ROPLL_REF According to the datasheet, setting the dig_clk_sel bit of CMN_REG(0097) to 1'b1 selects LCPLL as the reference clock, while setting it to 1'b0 selects the ROPLL. Signed-off-by: Damon Ding <damon.ding@...k-chips.com> --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index ceab9c71d3b5..0fecbb1df6fb 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -94,8 +94,8 @@ #define LCPLL_ALONE_MODE BIT(1) /* CMN_REG(0097) */ #define DIG_CLK_SEL BIT(1) -#define ROPLL_REF BIT(1) -#define LCPLL_REF 0 +#define LCPLL_REF BIT(1) +#define ROPLL_REF 0 /* CMN_REG(0099) */ #define CMN_ROPLL_ALONE_MODE BIT(2) #define ROPLL_ALONE_MODE BIT(2) -- 2.34.1
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