[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20241226-riscv-new-regset-v3-1-f5b96465826b@coelacanthus.name>
Date: Thu, 26 Dec 2024 18:45:09 +0800
From: Celeste Liu <uwu@...lacanthus.name>
To: Oleg Nesterov <oleg@...hat.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Eric Biederman <ebiederm@...ssion.com>,
Kees Cook <kees@...nel.org>, Shuah Khan <shuah@...nel.org>,
Albert Ou <aou@...s.berkeley.edu>
Cc: Alexandre Ghiti <alex@...ti.fr>, "Dmitry V. Levin" <ldv@...ace.io>,
Andrea Bolognani <abologna@...hat.com>,
Björn Töpel <bjorn@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>, Ron Economos <re@...z.net>,
Charlie Jenkins <charlie@...osinc.com>,
Andrew Jones <ajones@...tanamicro.com>, Quan Zhou <zhouquan@...as.ac.cn>,
Felix Yan <felixonmars@...hlinux.org>, Ruizhe Pan <c141028@...il.com>,
Guo Ren <guoren@...nel.org>, Yao Zi <ziyao@...root.org>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-mm@...ck.org, linux-kselftest@...r.kernel.org,
Celeste Liu <uwu@...lacanthus.name>, stable@...r.kernel.org,
Björn Töpel <bjorn@...osinc.com>
Subject: [PATCH v3 1/2] riscv/ptrace: add new regset to access original a0
register
The orig_a0 is missing in struct user_regs_struct of riscv, and there is
no way to add it without breaking UAPI. (See Link tag below)
Like NT_ARM_SYSTEM_CALL do, we add a new regset name NT_RISCV_ORIG_A0 to
access original a0 register from userspace via ptrace API.
Fixes: e2c0cdfba7f6 ("RISC-V: User-facing API")
Link: https://lore.kernel.org/all/59505464-c84a-403d-972f-d4b2055eeaac@gmail.com/
Cc: stable@...r.kernel.org
Reviewed-by: Björn Töpel <bjorn@...osinc.com>
Signed-off-by: Celeste Liu <uwu@...lacanthus.name>
---
arch/riscv/kernel/ptrace.c | 32 ++++++++++++++++++++++++++++++++
include/uapi/linux/elf.h | 1 +
2 files changed, 33 insertions(+)
diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
index ea67e9fb7a583683b922fe2c017ea61f3bc848db..ef9ab74c8575a5c440155973b1c625c06a867c97 100644
--- a/arch/riscv/kernel/ptrace.c
+++ b/arch/riscv/kernel/ptrace.c
@@ -31,6 +31,7 @@ enum riscv_regset {
#ifdef CONFIG_RISCV_ISA_SUPM
REGSET_TAGGED_ADDR_CTRL,
#endif
+ REGSET_ORIG_A0,
};
static int riscv_gpr_get(struct task_struct *target,
@@ -184,6 +185,29 @@ static int tagged_addr_ctrl_set(struct task_struct *target,
}
#endif
+static int riscv_orig_a0_get(struct task_struct *target,
+ const struct user_regset *regset,
+ struct membuf to)
+{
+ return membuf_store(&to, task_pt_regs(target)->orig_a0);
+}
+
+static int riscv_orig_a0_set(struct task_struct *target,
+ const struct user_regset *regset,
+ unsigned int pos, unsigned int count,
+ const void *kbuf, const void __user *ubuf)
+{
+ unsigned long orig_a0 = task_pt_regs(target)->orig_a0;
+ int ret;
+
+ ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &orig_a0, 0, -1);
+ if (ret)
+ return ret;
+
+ task_pt_regs(target)->orig_a0 = orig_a0;
+ return 0;
+}
+
static const struct user_regset riscv_user_regset[] = {
[REGSET_X] = {
.core_note_type = NT_PRSTATUS,
@@ -224,6 +248,14 @@ static const struct user_regset riscv_user_regset[] = {
.set = tagged_addr_ctrl_set,
},
#endif
+ [REGSET_ORIG_A0] = {
+ .core_note_type = NT_RISCV_ORIG_A0,
+ .n = 1,
+ .size = sizeof(elf_greg_t),
+ .align = sizeof(elf_greg_t),
+ .regset_get = riscv_orig_a0_get,
+ .set = riscv_orig_a0_set,
+ },
};
static const struct user_regset_view riscv_user_native_view = {
diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
index b44069d29cecc0f9de90ee66bfffd2137f4275a8..390060229601631da2fb27030d9fa2142e676c14 100644
--- a/include/uapi/linux/elf.h
+++ b/include/uapi/linux/elf.h
@@ -452,6 +452,7 @@ typedef struct elf64_shdr {
#define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */
#define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */
#define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address control (prctl()) */
+#define NT_RISCV_ORIG_A0 0x903 /* RISC-V original a0 register */
#define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */
#define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */
#define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */
--
2.47.1
Powered by blists - more mailing lists