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Message-Id: <20241226-riscv-new-regset-v4-0-4496a29d0436@coelacanthus.name>
Date: Thu, 26 Dec 2024 18:52:50 +0800
From: Celeste Liu <uwu@...lacanthus.name>
To: Oleg Nesterov <oleg@...hat.com>, 
 Paul Walmsley <paul.walmsley@...ive.com>, 
 Palmer Dabbelt <palmer@...belt.com>, Eric Biederman <ebiederm@...ssion.com>, 
 Kees Cook <kees@...nel.org>, Shuah Khan <shuah@...nel.org>, 
 Albert Ou <aou@...s.berkeley.edu>
Cc: Alexandre Ghiti <alex@...ti.fr>, "Dmitry V. Levin" <ldv@...ace.io>, 
 Andrea Bolognani <abologna@...hat.com>, 
 Björn Töpel <bjorn@...nel.org>, 
 Thomas Gleixner <tglx@...utronix.de>, Ron Economos <re@...z.net>, 
 Charlie Jenkins <charlie@...osinc.com>, 
 Andrew Jones <ajones@...tanamicro.com>, Quan Zhou <zhouquan@...as.ac.cn>, 
 Felix Yan <felixonmars@...hlinux.org>, Ruizhe Pan <c141028@...il.com>, 
 Guo Ren <guoren@...nel.org>, Yao Zi <ziyao@...root.org>, 
 linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, 
 linux-mm@...ck.org, linux-kselftest@...r.kernel.org, 
 Celeste Liu <uwu@...lacanthus.name>, stable@...r.kernel.org, 
 Björn Töpel <bjorn@...osinc.com>
Subject: [PATCH v4 0/2] riscv/ptrace: add new regset to access original a0
 register

The orig_a0 is missing in struct user_regs_struct of riscv, and there is
no way to add it without breaking UAPI. (See Link tag below)

Like NT_ARM_SYSTEM_CALL do, we add a new regset name NT_RISCV_ORIG_A0 to
access original a0 register from userspace via ptrace API.

Link: https://lore.kernel.org/all/59505464-c84a-403d-972f-d4b2055eeaac@gmail.com/

Signed-off-by: Celeste Liu <uwu@...lacanthus.name>
---
Changes in v4:
- Fix a copy paste error in selftest. (Forget to commit...)
- Link to v3: https://lore.kernel.org/r/20241226-riscv-new-regset-v3-0-f5b96465826b@coelacanthus.name

Changes in v3:
- Use return 0 directly for readability.
- Fix test for modify a0.
- Add Fixes: tag
- Remove useless Cc: stable.
- Selftest will check both a0 and orig_a0, but depends on the
  correctness of PTRACE_GET_SYSCALL_INFO.
- Link to v2: https://lore.kernel.org/r/20241203-riscv-new-regset-v2-0-d37da8c0cba6@coelacanthus.name

Changes in v2:
- Fix integer width.
- Add selftest.
- Link to v1: https://lore.kernel.org/r/20241201-riscv-new-regset-v1-1-c83c58abcc7b@coelacanthus.name

---
Celeste Liu (2):
      riscv/ptrace: add new regset to access original a0 register
      riscv: selftests: Add a ptrace test to verify syscall parameter modification

 arch/riscv/kernel/ptrace.c                   |  32 ++++++
 include/uapi/linux/elf.h                     |   1 +
 tools/testing/selftests/riscv/abi/.gitignore |   1 +
 tools/testing/selftests/riscv/abi/Makefile   |   5 +-
 tools/testing/selftests/riscv/abi/ptrace.c   | 151 +++++++++++++++++++++++++++
 5 files changed, 189 insertions(+), 1 deletion(-)
---
base-commit: 0e287d31b62bb53ad81d5e59778384a40f8b6f56
change-id: 20241201-riscv-new-regset-d529b952ad0d

Best regards,
-- 
Celeste Liu <uwu@...lacanthus.name>


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