linux-kernel - Re: [PATCH v6] i2c: imx-lpi2c: add eDMA mode support for LPI2C

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Message-ID: <ly7mzakvws75xcjncm6x24rie4xewt6ll4dlkz2kl5cblihi6n@7kivy2uqdwvp>
Date: Fri, 27 Dec 2024 01:38:23 +0100
From: Andi Shyti <andi.shyti@...nel.org>
To: carlos.song@....com
Cc: aisheng.dong@....com, shawnguo@...nel.org, s.hauer@...gutronix.de, 
	kernel@...gutronix.de, festevam@...il.com, sumit.semwal@...aro.org, 
	christian.koenig@....com, frank.li@....com, linux-i2c@...r.kernel.org, imx@...ts.linux.dev, 
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, linux-media@...r.kernel.org, 
	dri-devel@...ts.freedesktop.org, linaro-mm-sig@...ts.linaro.org
Subject: Re: [PATCH v6] i2c: imx-lpi2c: add eDMA mode support for LPI2C

Hi Carlos,

On Mon, Nov 25, 2024 at 10:29:09PM +0800, carlos.song@....com wrote:
> From: Carlos Song <carlos.song@....com>
> 
> Add eDMA mode support for LPI2C.
> 
> There are some differences between TX DMA mode and RX DMA mode.
> LPI2C MTDR register is Controller Transmit Data Register.
> When lpi2c send data, it is tx cmd register and tx data fifo.
> When lpi2c receive data, it is just a rx cmd register. LPI2C MRDR
> register is Controller Receive Data Register, received data are
> stored in this.
> 
> MTDR[8:10] is CMD field and MTDR[0:7] is DATA filed.
> +-----------+-------------------------------+
> |  C  M  D  |          D  A  T  A           |
> +---+---+---+---+---+---+---+---+---+---+---+
> | 10| 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
> +---+---+---+---+---+---+---+---+---+---+---+
> 
> MRDR is Controller Receive Data Register.
> MRDR[0:7] is DATA filed.
> +-------------------------------+
> |          D  A  T  A           |
> +---+---+---+---+---+---+---+---+
> | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
> +---+---+---+---+---+---+---+---+
> 
> When the LPI2C controller needs to send data, tx cmd and 8-bit data
> should be written into MTDR:
> CMD: 000b: Transmit the value in DATA[7:0].
> DATA: 8-bit data.
> 
> If lpi2c controller needs to send N 8-bit data, just write N times
> (CMD(W) + DATA(u8)) to MTDR.
> 
> When the LPI2C controller needs to receive data, rx cmd should be
> written into MTDR, the received data will be stored in the MRDR.
> 
> MTDR(CMD): 001b: Receive (DATA[7:0] + 1) 8-bit data.
> MTDR(DATA): byte counter.
> MRDR(DATA): 8-bit data.
> 
> So when lpi2c controller needs to receive N 8-bit data,
> 1. N <= 256:
> Write 1 time (CMD(R) + BYTE COUNT(N-1)) into MTDR and receive data from
> MRDR.
> 2. N > 256:
> Write N/256 times (CMD(R) + BYTE COUNT(255)) + 1 time (CMD(R) + BYTE
> COUNT(N%256)) into MTDR and receive data from MRDR.
> 
> Due to these differences, when lpi2c is in DMA TX mode, only enable TX
> channel to send data. But when lpi2c is in DMA RX mode, TX and RX channel
> are both enabled, TX channel is used to send RX cmd and RX channel is
> used to receive data.
> 
> Signed-off-by: Carlos Song <carlos.song@....com>
> Signed-off-by: Frank Li <frank.li@....com>

merged to i2c/i2c-host.

Thanks,
Andi