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Message-ID: <z7jb32foci6bamqqddkkp34hazi2itp6uclarsoi5pkrgso2go@bxflagkaciq6>
Date: Fri, 27 Dec 2024 09:28:23 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Kever Yang <kever.yang@...k-chips.com>
Cc: heiko@...ech.de, linux-rockchip@...ts.infradead.org,
Finley Xiao <finley.xiao@...k-chips.com>, Liang Chen <cl@...k-chips.com>, devicetree@...r.kernel.org,
Conor Dooley <conor+dt@...nel.org>, Michael Turquette <mturquette@...libre.com>,
Rob Herring <robh@...nel.org>, Stephen Boyd <sboyd@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>, linux-kernel@...r.kernel.org,
Krzysztof Kozlowski <krzk+dt@...nel.org>, linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 2/3] dt-bindings: clock, reset: rockchip: Add support
for rk3562
On Tue, Dec 24, 2024 at 05:23:09PM +0800, Kever Yang wrote:
> From: Finley Xiao <finley.xiao@...k-chips.com>
>
> Add the dt-bindings header for the rk3562, that gets shared between
> the clock controller and the clock references in the dts.
> Add softreset ID for rk3562.
>
> Signed-off-by: Finley Xiao <finley.xiao@...k-chips.com>
> Signed-off-by: Liang Chen <cl@...k-chips.com>
> Signed-off-by: Kever Yang <kever.yang@...k-chips.com>
> ---
>
> Changes in v2:
> - rename the file to rockchip,rk3562-cru.h
> - remove CLK_NR_CLKS
> - add new file for reset ID
> - update to use dual license
>
> .../dt-bindings/clock/rockchip,rk3562-cru.h | 377 ++++++++++++++++++
> .../dt-bindings/reset/rockchip,rk3562-cru.h | 360 +++++++++++++++++
No, that's not a separate patch. Headers *ALWAYS* go with the bindings
patch.
> 2 files changed, 737 insertions(+)
> create mode 100644 include/dt-bindings/clock/rockchip,rk3562-cru.h
> create mode 100644 include/dt-bindings/reset/rockchip,rk3562-cru.h
>
> diff --git a/include/dt-bindings/clock/rockchip,rk3562-cru.h b/include/dt-bindings/clock/rockchip,rk3562-cru.h
> new file mode 100644
> index 000000000000..ad07ad3a12ad
> --- /dev/null
> +++ b/include/dt-bindings/clock/rockchip,rk3562-cru.h
> @@ -0,0 +1,377 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
Why not using license requested by checkpatch?
> +/*
> + * Copyright (c) 2022-2024 Rockchip Electronics Co., Ltd.
> + * Author: Finley Xiao <finley.xiao@...k-chips.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H
> +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H
> +
> +/* cru-clocks indices */
> +
> +/* cru plls */
> +#define PLL_APLL 1
Start with 0. Your other binding also starts with 0, so be consistent.
> +#define PLL_GPLL 2
> +#define PLL_VPLL 3
> +#define PLL_HPLL 4
> +#define PLL_CPLL 5
> +#define PLL_DPLL 6
> +
> +/* cru clocks */
Missing clock for 7. You are not supposed to have any holes here.
> +#define ARMCLK 8
> +#define CLK_GPU 9
> +#define ACLK_RKNN 10
Best regards,
Krzysztof
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