linux-kernel - Re: [PATCH 1/2] dt-bindings: gpio: add binding doc for siflower,sf19a2890-gpio

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CACRpkdZ8Yve3EPB6E1nrPi0se=rgush60Q=Vce4Ux2w1QW3w_w@mail.gmail.com>
Date: Fri, 27 Dec 2024 17:45:43 +0100
From: Linus Walleij <linus.walleij@...aro.org>
To: Chuanhong Guo <gch981213@...il.com>
Cc: linux-gpio@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Bartosz Golaszewski <brgl@...ev.pl>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Philipp Zabel <p.zabel@...gutronix.de>, Qingfang Deng <qingfang.deng@...lower.com.cn>
Subject: Re: [PATCH 1/2] dt-bindings: gpio: add binding doc for siflower,sf19a2890-gpio

Hi Chuanhong,

thanks for your patch!

On Wed, Dec 25, 2024 at 4:59 AM Chuanhong Guo <gch981213@...il.com> wrote:

> Add dt binding doc for the GPIO controller found on Siflower SF19A2890
> and various other Siflower MIPS and RISC-V SoCs.
>
> Signed-off-by: Chuanhong Guo <gch981213@...il.com>
(...)
> +  interrupts:
> +    description:
> +      Interrupt mapping, one interrupt per 16 GPIOs.

So from the driver it is very clear that this is lumping together several
GPIO blocks with 16 GPIOs in each into a bigger GPIO controller, despite
the instances are identical. They even each have an individual IRQ.

> +  ngpios:
> +    description:
> +      The number of GPIOs available on the controller implementation.
> +    minimum: 1

I would say minimum: 1 maximum: 16 default: 16.

One instance per block/bank.

> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/interrupt-controller/mips-gic.h>
> +    gpio@...00000 {
> +      compatible = "siflower,sf19a2890-gpio";
> +      reg = <0x19d00000 0x100000>;

Just use 4 instances. Since (looking at the driver) it seems there
is an IRQ register that is "off the bulk" I would do something like:

instance 0:

reg = <0x19d00000 0x40>, <0x19d04000 4>;

instance: 1:

reg = <0x19d00040 0x40>, <0x19d04004 4>;

(...etc...)

You can add reg-names if you don't want the implicit order
of registers. (Perhaps the bindings maintainers will push for this
as well.)

> +      interrupts = <GIC_SHARED 246 IRQ_TYPE_LEVEL_HIGH>,
> +        <GIC_SHARED 247 IRQ_TYPE_LEVEL_HIGH>,
> +        <GIC_SHARED 248 IRQ_TYPE_LEVEL_HIGH>,
> +        <GIC_SHARED 249 IRQ_TYPE_LEVEL_HIGH>;

Just one IRQ and handle just one block per instance.

> +      clocks = <&gpioclk 0>;
> +      resets = <&gpiorst 0>;
> +
> +      gpio-controller;
> +      #gpio-cells = <2>;
> +      ngpios = <49>;

Just omit this on instances 0,1,2 and set to 1 on
instance 3.

> +      gpio-ranges = <&pinctrl 0 0 49>;

Augment this accordingly to one instance per bank/range.

Yours,
Linus Walleij