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Message-ID: <ru3xpse4mg62gcxemut3zro6qw6v6firjnefo57k74n2ti66ym@l3pe2hpz5csl>
Date: Mon, 30 Dec 2024 14:33:06 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Damon Ding <damon.ding@...k-chips.com>
Cc: heiko@...ech.de, robh@...nel.org, krzk+dt@...nel.org, 
	conor+dt@...nel.org, rfoss@...nel.org, vkoul@...nel.org, 
	sebastian.reichel@...labora.com, cristian.ciocaltea@...labora.com, l.stach@...gutronix.de, 
	andy.yan@...k-chips.com, hjc@...k-chips.com, algea.cao@...k-chips.com, 
	kever.yang@...k-chips.com, dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org, 
	linux-phy@...ts.infradead.org
Subject: Re: [PATCH v4 04/17] phy: phy-rockchip-samsung-hdptx: Swap the
 definitions of LCPLL_REF and ROPLL_REF

On Thu, Dec 26, 2024 at 02:33:00PM +0800, Damon Ding wrote:
> According to the datasheet, setting the dig_clk_sel bit of CMN_REG(0097)
> to 1'b1 selects LCPLL as the reference clock, while setting it to 1'b0
> selects the ROPLL.
> 
> Signed-off-by: Damon Ding <damon.ding@...k-chips.com>
> ---
>  drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>

-- 
With best wishes
Dmitry

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