lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <52fa8219-0485-4fc6-8f3f-5759649057cf@quicinc.com>
Date: Mon, 30 Dec 2024 21:04:39 +0530
From: Kathiravan Thirumoorthy <quic_kathirav@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
        Manikanta Mylavarapu
	<quic_mmanikan@...cinc.com>,
        <andersson@...nel.org>, <linus.walleij@...aro.org>, <robh@...nel.org>,
        <krzk+dt@...nel.org>, <conor+dt@...nel.org>, <konradybcio@...nel.org>,
        <mturquette@...libre.com>, <sboyd@...nel.org>,
        <linux-arm-msm@...r.kernel.org>, <linux-gpio@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-clk@...r.kernel.org>
CC: <quic_varada@...cinc.com>, <quic_srichara@...cinc.com>
Subject: Re: [PATCH v3 0/6] Add SPI4 support for IPQ5424



On 12/30/2024 7:28 PM, Konrad Dybcio wrote:
> On 30.12.2024 2:54 PM, Konrad Dybcio wrote:
>> On 30.12.2024 7:51 AM, Kathiravan Thirumoorthy wrote:
>>>
>>>
>>> On 12/27/2024 12:54 PM, Manikanta Mylavarapu wrote:
>>>> Add SPI4 node to the IPQ5424 device tree and update the relevant
>>>> bindings, GPIO pin mappings accordingly.
>>>>
>>>> Changes in V3:
>>>>      - Rename SPI0 to SPI4 because SPI protocol runs on serial engine 4
>>>
>>> Do we really need to do this? If so, it will not align with the HW documentation and will lead to the confusion down the line. IMHO, we should stick with the convention followed in the HW documentation.
>>
>> +1, the clocks are called SPI0/SPI1 internally
> 
> Ok, I looked at a bit more documentation and it looks like
> somebody just had fun naming things..
> 
> SPI0 is on SE4 and SPI1 is on something else, with no more
> clock provisions for that protocol.. Which is not usually the
> case.


IPQ5424 has one QUPV3 instance with 6 SEs. SE0-SE4 are Mini core and SE5 
is FW core.

SE0 and SE1 are for 4-wire UART and 2-wire UART respectively. SE2 and 
SE3 are for I2C protocol. SE4 is for SPI.

Since SE5 is FW based (some RDPs use this SE for I2C). In GCC block, 
clocks for this instance is named after SPI as SPI1.


> 
> Let's just go with what you guys use internally, as this is
> mighty spaghetti
> 
> Konrad

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ