linux-kernel - Re: [PATCH 11/12] x86/mm: enable AMD translation cache extensions

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Message-Id: <40C8627F-0B0B-4F19-8FF8-5D852A5F9F0F@gmail.com>
Date: Mon, 30 Dec 2024 20:25:40 +0200
From: Nadav Amit <nadav.amit@...il.com>
To: Rik van Riel <riel@...riel.com>
Cc: the arch/x86 maintainers <x86@...nel.org>,
 Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
 kernel-team@...a.com,
 Dave Hansen <dave.hansen@...ux.intel.com>,
 luto@...nel.org,
 peterz@...radead.org,
 Thomas Gleixner <tglx@...utronix.de>,
 Ingo Molnar <mingo@...hat.com>,
 Borislav Petkov <bp@...en8.de>,
 "H. Peter Anvin" <hpa@...or.com>,
 Andrew Morton <akpm@...ux-foundation.org>,
 zhengqi.arch@...edance.com,
 "open list:MEMORY MANAGEMENT" <linux-mm@...ck.org>
Subject: Re: [PATCH 11/12] x86/mm: enable AMD translation cache extensions

> On 30 Dec 2024, at 19:53, Rik van Riel <riel@...riel.com> wrote:
> 
> --- a/arch/x86/kernel/cpu/amd.c
> +++ b/arch/x86/kernel/cpu/amd.c
> @@ -1143,6 +1143,14 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
> 
> 	/* Max number of pages INVLPGB can invalidate in one shot */
> 	invlpgb_count_max = (edx & 0xffff) + 1;
> +
> +	/* If supported, enable translation cache extensions (TCE) */
> +	cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
> +	if (ecx & BIT(17)) {
> +		u64 msr = native_read_msr(MSR_EFER);;
> +		msr |= BIT(15);
> +		wrmsrl(MSR_EFER, msr);
> +	}
> }

Sorry for the gradual/delayed feedback.

Is it possible to avoid the BIT(x) and just add the bits to 
arch/x86/include/asm/msr-index.h like EFER_FFXSR ?