lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <743d9eb4-a7ee-4ce7-91a8-52ddcd353bb2@kernel.org>
Date: Tue, 31 Dec 2024 08:43:11 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Devang Tailor <dev.tailor@...sung.com>, alim.akhtar@...sung.com,
 robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: add cpu cache information to ExynosAuto-v920

On 31/12/2024 07:43, Devang Tailor wrote:
>  
>  		cpu9: cpu@...00 {
> @@ -152,6 +215,22 @@ cpu9: cpu@...00 {
>  			compatible = "arm,cortex-a78ae";
>  			reg = <0x0 0x20100>;
>  			enable-method = "psci";
> +			i-cache-size = <0x10000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <0x10000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <256>;
> +			next-level-cache = <&cpu_l2>;
> +		};
> +
> +		cpu_l2: l2-cache0 {

Are there more l2-caches? '0' suggests that, so please add nodes for all
of them.



Best regards,
Krzysztof

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ