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Message-ID: <20250102120544.1407152-1-s-k6@ti.com>
Date: Thu, 2 Jan 2025 17:35:44 +0530
From: Santhosh Kumar K <s-k6@...com>
To: <broonie@...nel.org>
CC: <linux-spi@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<vigneshr@...com>, <p-mantena@...com>, <s-k6@...com>
Subject: [PATCH] spi: cadence-quadspi: Enable SPI_TX_QUAD
Enable the SPI_TX_QUAD mode bit in the host->mode_bits to support
data transmission over four lines to improve the performance.
Tested the functionality on AM62Lx EVM (W25N01JW) in 1S-4S-4S mode.
Signed-off-by: Santhosh Kumar K <s-k6@...com>
---
Repo: https://github.com/santhosh21/linux/tree/uL_next
Test results: https://gist.github.com/santhosh21/71ab6646dccc238a0b3c47c0382f219a
Regards,
Santhosh.
drivers/spi/spi-cadence-quadspi.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 47477f2d9a25..594408d53400 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -49,6 +49,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_CS_CNT_MAX);
/* Capabilities */
#define CQSPI_SUPPORTS_OCTAL BIT(0)
+#define CQSPI_SUPPORTS_QUAD BIT(1)
#define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0)
@@ -1888,6 +1889,8 @@ static int cqspi_probe(struct platform_device *pdev)
cqspi->master_ref_clk_hz);
if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
host->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
+ if (ddata->hwcaps_mask & CQSPI_SUPPORTS_QUAD)
+ host->mode_bits |= SPI_TX_QUAD;
if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) {
cqspi->use_direct_mode = true;
cqspi->use_direct_mode_wr = true;
@@ -2062,7 +2065,7 @@ static const struct cqspi_driver_platdata k2g_qspi = {
};
static const struct cqspi_driver_platdata am654_ospi = {
- .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
+ .hwcaps_mask = CQSPI_SUPPORTS_OCTAL | CQSPI_SUPPORTS_QUAD,
.quirks = CQSPI_NEEDS_WR_DELAY,
};
--
2.34.1
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