linux-kernel - Re: [PATCH 0/2] riscv,aplic: support for hart indexes

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Message-ID: <CAAhSdy3oL3doCANZLv4i9Z0v4ui82AC0oAAMnHkpnkMCS-EZNA@mail.gmail.com>
Date: Thu, 2 Jan 2025 20:49:19 +0530
From: Anup Patel <anup@...infault.org>
To: Vladimir Kondratiev <Vladimir.Kondratiev@...ileye.com>
Cc: Thomas Gleixner <tglx@...utronix.de>, Paul Walmsley <paul.walmsley@...ive.com>, 
	Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>, 
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 0/2] riscv,aplic: support for hart indexes

On Thu, Jan 2, 2025 at 8:37 PM Vladimir Kondratiev
<Vladimir.Kondratiev@...ileye.com> wrote:
>
> >Here's the text from "4.8 Interrupt delivery directly by the APLIC" of
> >the AIA specification:
>
> >"When an interrupt domain is in direct delivery mode (domaincfg.DM = 0),
> >interrupts are delivered from the APLIC to harts by a unique signal to each
> >hart, usually a dedicated wire. In this case, the domain’s memory-mapped
> >control region contains at the end an array of interrupt delivery control (IDC)
> >structures, one IDC structure per potential hart index. The first IDC structure
> >is for the domain’s hart with index 0; the second is for the hart with
> >index 1; etc."
>
> >The AIA spec clearly says that for APLIC in direct mode requires
> >sequential "HART index" starting from 0 so that IDC structures can
> >be located using the APLIC "HART index".
>
> Hi Anup,
> I am reading same text but interpreting it differently. I understand it this way:
> for every hart, there's "hart index" that may be arbitrary (unique in domain)
> 14-bit  integer. Then IDC should be accessed using this index. I don't see
> anything that prohibits sparse array of IDCs.
>
> To support this, #4.5 "Memory-mapped control region for an interrupt domain" says:
>
> The array of IDC structures may include some for potential hart index numbers that are not actual
> hart index numbers in the domain. For example, the first IDC structure is always for hart index 0,
> but 0 is not necessarily a valid index number for any hart in the domain. For each IDC structure in
> the array that does not correspond to a valid hart index number in the domain, the IDC structure’s
> registers may (or may not) be all read-only zeros.
>
> This suggests 0 may be not a valid hart index, so clearly some gaps are allowed.

I see your point and this is a fair interpretation.
I will review other patches.

Thanks,
Anup