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Message-ID: <da83df12-d7e2-41fe-a303-290640e2a4a4@shopee.com>
Date: Thu, 2 Jan 2025 11:53:05 +0800
From: Haifeng Xu <haifeng.xu@...pee.com>
To: Tony Nguyen <anthony.l.nguyen@...el.com>,
", Przemek Kitszel" <przemyslaw.kitszel@...el.com>,
", \"David S. Miller\"" <davem@...emloft.net>,
", Eric Dumazet" <edumazet@...gle.com>, ", Jakub Kicinski"
<kuba@...nel.org>, ", Paolo Abeni" <pabeni@...hat.com>
Cc: linux-kernel@...r.kernel.org, netdev@...r.kernel.org,
intel-wired-lan@...ts.osuosl.org
Subject: [Question] ixgbe:Mechanism of RSS
Hi masters,
We use the Intel Corporation 82599ES NIC in our production environment. And it has 63 rx queues, every rx queue interrupt is processed by a single cpu.
The RSS configuration can be seen as follow:
RX flow hash indirection table for eno5 with 63 RX ring(s):
0: 0 1 2 3 4 5 6 7
8: 8 9 10 11 12 13 14 15
16: 0 1 2 3 4 5 6 7
24: 8 9 10 11 12 13 14 15
32: 0 1 2 3 4 5 6 7
40: 8 9 10 11 12 13 14 15
48: 0 1 2 3 4 5 6 7
56: 8 9 10 11 12 13 14 15
64: 0 1 2 3 4 5 6 7
72: 8 9 10 11 12 13 14 15
80: 0 1 2 3 4 5 6 7
88: 8 9 10 11 12 13 14 15
96: 0 1 2 3 4 5 6 7
104: 8 9 10 11 12 13 14 15
112: 0 1 2 3 4 5 6 7
120: 8 9 10 11 12 13 14 15
The maximum number of RSS queues is 16. So I have some questions about this. Will other cpus except 0~15 receive the rx interrupts?
In our production environment, cpu 16~62 also receive the rx interrupts. Was our RSS misconfigured?
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