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Message-ID: <a017543d-a27e-466e-bf51-9eb7e70ab215@linaro.org>
Date: Thu, 2 Jan 2025 19:57:56 +0200
From: Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>
To: Bryan O'Donoghue <bryan.odonoghue@...aro.org>,
Loic Poulain <loic.poulain@...aro.org>, Robert Foss <rfoss@...nel.org>,
Andi Shyti <andi.shyti@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Todor Tomov <todor.too@...il.com>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd
<sboyd@...nel.org>, Jagadeesh Kona <quic_jkona@...cinc.com>,
Konrad Dybcio <konradybcio@...nel.org>
Cc: linux-i2c@...r.kernel.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-media@...r.kernel.org, linux-clk@...r.kernel.org,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH v3 5/6] arm64: dts: qcom: x1e80100: Add CCI definitions
Hi Bryan.
On 1/2/25 18:32, Bryan O'Donoghue wrote:
> Add in 2 CCI busses. One bus has two CCI bus master pinouts:
> cci_i2c_scl0 = gpio101
> cci_i2c_sda0 = gpio102
> cci_i2c_scl1 = gpio103
> cci_i2c_sda1 = gpio104
>
> A second bus has a single CCI bus master pinout:
> cci_i2c_scl2 = gpio105
> cci_i2c_sda2 = gpio106
I notice that the change assigns "aon_cci" function to gpio235 and gpio236
pins, and they do serve as cci1_i2c1 sda/scl pins, thus here is the second
CCI bus master.
So, I assume the commit message is not correct...
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
> ---
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 150 +++++++++++++++++++++++++++++++++
> 1 file changed, 150 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index 5c7b0c048d41a4ba3d74bbf77216ad09b652ed30..97ebf5596dfc3caa920ef85722ca8afd49cd3c24 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -4648,6 +4648,84 @@ usb_1_ss1_dwc3_ss: endpoint {
> };
> };
>
> + cci0: cci@...5000 {
> + compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci";
> + reg = <0 0x0ac15000 0 0x1000>;
> +
> + interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CCI_0_CLK>;
> + clock-names = "camnoc_axi",
> + "cpas_ahb",
> + "cci";
> +
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> + pinctrl-0 = <&cci0_default>;
> + pinctrl-1 = <&cci0_sleep>;
> + pinctrl-names = "default", "sleep";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + cci0_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci0_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + cci1: cci@...6000 {
> + compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci";
> + reg = <0 0x0ac16000 0 0x1000>;
> +
> + interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CCI_1_CLK>;
> + clock-names = "camnoc_axi",
> + "cpas_ahb",
> + "cci";
> +
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> + pinctrl-0 = <&cci1_default>;
> + pinctrl-1 = <&cci1_sleep>;
> + pinctrl-names = "default", "sleep";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + cci1_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci1_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> camcc: clock-controller@...0000 {
> compatible = "qcom,x1e80100-camcc";
> reg = <0 0x0ade0000 0 0x20000>;
> @@ -5271,6 +5349,78 @@ tlmm: pinctrl@...0000 {
> gpio-ranges = <&tlmm 0 0 239>;
> wakeup-parent = <&pdc>;
>
> + cci0_default: cci0-default-state {
> + cci0_i2c0_default: cci0-i2c0-default-pins {
> + /* cci_i2c_sda0, cci_i2c_scl0 */
> + pins = "gpio101", "gpio102";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + cci0_i2c1_default: cci0-i2c1-default-pins {
> + /* cci_i2c_sda1, cci_i2c_scl1 */
> + pins = "gpio103", "gpio104";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci0_sleep: cci0-sleep-state {
> + cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
> + /* cci_i2c_sda0, cci_i2c_scl0 */
> + pins = "gpio101", "gpio102";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
> + /* cci_i2c_sda1, cci_i2c_scl1 */
> + pins = "gpio103", "gpio104";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + cci1_default: cci1-default-state {
> + cci1_i2c0_default: cci1-i2c0-default-pins {
> + /* cci_i2c_sda2, cci_i2c_scl2 */
> + pins = "gpio105","gpio106";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + cci1_i2c1_default: cci1-i2c1-default-pins {
> + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */
> + pins = "gpio235","gpio236";
> + function = "aon_cci";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci1_sleep: cci1-sleep-state {
> + cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
> + /* cci_i2c_sda2, cci_i2c_scl2 */
> + pins = "gpio105","gpio106";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
> + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */
> + pins = "gpio235","gpio236";
> + function = "aon_cci";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> qup_i2c0_data_clk: qup-i2c0-data-clk-state {
> /* SDA, SCL */
> pins = "gpio0", "gpio1";
>
--
Best wishes,
Vladimir
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