linux-kernel - [PATCH v1 0/5] riscv: dts: starfive: jh7110-common: Sync downstream U-Boot changes

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Message-ID: <20250102194530.418127-1-e@freeshell.de>
Date: Thu,  2 Jan 2025 11:45:06 -0800
From: E Shattow <e@...eshell.de>
To: Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>
Cc: linux-kernel@...r.kernel.org,
	E Shattow <e@...eshell.de>,
	linux-riscv@...ts.infradead.org
Subject: [PATCH v1 0/5] riscv: dts: starfive: jh7110-common: Sync downstream U-Boot changes

U-Boot boot loader has adopted using the Linux dt-rebasing tree for dts
with JH7110 VisionFive2 board target (and related JH7110 common boards).
Sync the minimum changes from jh7110-common.dtsi needed for boot so these
can be dropped from U-Boot.

E Shattow (5):
  riscv: dts: starfive: jh7110-common: replace syscrg clock assignments
  riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2
    cycles max 100MHz
  riscv: dts: starfive: jh7110-common: assign 24MHz clock-frequency to
    uart0
  riscv: dts: starfive: jh7110-common: add eeprom node to i2c5
  riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by
    boot loader

 .../boot/dts/starfive/jh7110-common.dtsi      | 29 +++++++++++++++----
 1 file changed, 24 insertions(+), 5 deletions(-)


base-commit: 708d55db3edbe2ccf88d94b5f2e2b404bc0ba37c
-- 
2.45.2