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Message-ID: <20250103211446.GA4063@bhelgaas>
Date: Fri, 3 Jan 2025 15:14:46 -0600
From: Bjorn Helgaas <helgaas@...nel.org>
To: Nícolas F. R. A. Prado <nfraprado@...labora.com>
Cc: Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
kernel@...labora.com, Chen-Yu Tsai <wenst@...omium.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-mediatek@...ts.infradead.org
Subject: Re: [PATCH v4 14/19] arm64: dts: mediatek: asurada: Enable PCIe and
add WiFi
On Wed, Jun 29, 2022 at 11:59:51AM -0400, Nícolas F. R. A. Prado wrote:
> Enable MT8192's PCIe controller and add support for the MT7921e WiFi
> card that is present on that bus for the Asurada platform.
> +&pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie_pins>;
> +
> + pcie0: pcie@0,0 {
> + device_type = "pci";
> + reg = <0x0000 0 0 0 0>;
> + num-lanes = <1>;
> + bus-range = <0x1 0x1>;
Hi Nícolas, what's the purpose of this bus-range? IIUC this describes
a Root Port, where we can read and configure the secondary/subordinate
bus numbers from the RP config space, so it seems like we don't need
to describe them here.
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> +
> + wifi: wifi@0,0 {
> + reg = <0x10000 0 0 0 0x100000>,
> + <0x10000 0 0x100000 0 0x100000>;
> + memory-region = <&wifi_restricted_dma_region>;
> + };
> + };
> +};
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