linux-kernel - Re: [PATCH v3 3/4] dt-bindings: pinctrl: sunxi: Add gpio-reserved-ranges property

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20250103235600.7834a6a6@minigeek.lan>
Date: Fri, 3 Jan 2025 23:56:00 +0000
From: Andre Przywara <andre.przywara@....com>
To: Lukas Schmid <lukas.schmid@...cube.li>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, Chen-Yu Tsai <wens@...e.org>, Jernej
 Skrabec <jernej.skrabec@...il.com>, Samuel Holland <samuel@...lland.org>,
 Linus Walleij <linus.walleij@...aro.org>, Maxime Ripard
 <mripard@...nel.org>, devicetree@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-sunxi@...ts.linux.dev,
 linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org
Subject: Re: [PATCH v3 3/4] dt-bindings: pinctrl: sunxi: Add
 gpio-reserved-ranges property

On Fri,  3 Jan 2025 20:45:19 +0000
Lukas Schmid <lukas.schmid@...cube.li> wrote:

Hi,

You would definitely need some text here, at the very least this "90"
deserves some comment.
But what is this property meant to say, actually? Looking at the DT I
guess you want to mark GPIOs as not connected/exposed or such? I don't
think this is the intended purpose of this property, it's more for
describing ranges of GPIOs not implemented in the GPIO *controller* -
say there are 18 pins on PortA, but pins 9-12 are not implemented (no
registers) - check Documentation/devicetree/bindings/gpio/gpio.txt.
But keep in mind that the Allwinner pinctrl device does not use this
kind of per-port binding in the first place, and I wouldn't know of any
SoC having non-consecutive pins per port anyway.

So I think this is not needed, not in this binding, and not in the DT.

Cheers,
Andre

P.S. Feel free to discuss things in replies to emails - that's why we
have those mails. In the past you seemed to always answer very quickly
with a new series, even though you seemed to disagree on some things
(RTC?)

> Signed-off-by: Lukas Schmid <lukas.schmid@...cube.li>
> ---
>  .../bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml        | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
> index 450240570314..24b90a5538d6 100644
> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
> @@ -83,6 +83,11 @@ properties:
>  
>    gpio-controller: true
>    interrupt-controller: true
> +
> +  gpio-reserved-ranges:
> +    minItems: 1
> +    maxItems: 90
> +
>    gpio-line-names: true
>  
>    input-debounce: