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Message-ID: <acdf1267-ce56-4ec1-8407-a5f3212a8bfe@quicinc.com>
Date: Fri, 3 Jan 2025 09:51:23 +0530
From: Imran Shaik <quic_imrashai@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>
CC: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd
<sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski
<krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Ajit Pandey
<quic_ajipan@...cinc.com>,
Taniya Das <quic_tdas@...cinc.com>,
Jagadeesh Kona
<quic_jkona@...cinc.com>,
Satya Priya Kakitapalli
<quic_skakitap@...cinc.com>,
<linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
Dmitry Baryshkov
<dmitry.baryshkov@...aro.org>
Subject: Re: [PATCH v3 2/6] clk: qcom: Add support for GPU Clock Controller on
QCS8300
On 12/27/2024 9:54 AM, Bjorn Andersson wrote:
> On Wed, Nov 06, 2024 at 03:21:57PM +0530, Imran Shaik wrote:
>> Add support to the QCS8300 GPU clock controller by extending
>> the SA8775P GPU clock controller, which is mostly identical
>> but QCS8300 has few additional clocks and minor differences.
>>
>
> What does "mostly identical" mean?
>
> Is QCS8300 a derivative of SA8775P? Or is it just by accident that these
> two SoCs happens to have almost the same set of clocks?
>
Yes, QCS8300 is a derivative of SA8775P.
>
> Also, commit messages should follow the flow described in
> https://docs.kernel.org/process/submitting-patches.html#describe-your-changes.
>
Sure, I will update the commit text with above details and post next series.
Thanks,
Imran
> Regards,
> Bjorn
>
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
>> Signed-off-by: Imran Shaik <quic_imrashai@...cinc.com>
>> ---
>> drivers/clk/qcom/gpucc-sa8775p.c | 49 +++++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 48 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c
>> index f8a8ac343d70..78cad622cb5a 100644
>> --- a/drivers/clk/qcom/gpucc-sa8775p.c
>> +++ b/drivers/clk/qcom/gpucc-sa8775p.c
>> @@ -12,7 +12,7 @@
>> #include <linux/platform_device.h>
>> #include <linux/regmap.h>
>>
>> -#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
>> +#include <dt-bindings/clock/qcom,qcs8300-gpucc.h>
>>
>> #include "clk-alpha-pll.h"
>> #include "clk-branch.h"
>> @@ -317,6 +317,24 @@ static struct clk_branch gpu_cc_crc_ahb_clk = {
>> },
>> };
>>
>> +static struct clk_branch gpu_cc_cx_accu_shift_clk = {
>> + .halt_reg = 0x95e8,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x95e8,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(const struct clk_init_data){
>> + .name = "gpu_cc_cx_accu_shift_clk",
>> + .parent_hws = (const struct clk_hw*[]){
>> + &gpu_cc_xo_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> static struct clk_branch gpu_cc_cx_ff_clk = {
>> .halt_reg = 0x914c,
>> .halt_check = BRANCH_HALT,
>> @@ -420,6 +438,24 @@ static struct clk_branch gpu_cc_demet_clk = {
>> },
>> };
>>
>> +static struct clk_branch gpu_cc_gx_accu_shift_clk = {
>> + .halt_reg = 0x95e4,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x95e4,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(const struct clk_init_data){
>> + .name = "gpu_cc_gx_accu_shift_clk",
>> + .parent_hws = (const struct clk_hw*[]){
>> + &gpu_cc_xo_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
>> .halt_reg = 0x7000,
>> .halt_check = BRANCH_HALT_VOTED,
>> @@ -499,6 +535,7 @@ static struct clk_regmap *gpu_cc_sa8775p_clocks[] = {
>> [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
>> [GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr,
>> [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
>> + [GPU_CC_CX_ACCU_SHIFT_CLK] = NULL,
>> [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
>> [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
>> [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
>> @@ -508,6 +545,7 @@ static struct clk_regmap *gpu_cc_sa8775p_clocks[] = {
>> [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
>> [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
>> [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
>> + [GPU_CC_GX_ACCU_SHIFT_CLK] = NULL,
>> [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
>> [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
>> [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
>> @@ -583,6 +621,7 @@ static const struct qcom_cc_desc gpu_cc_sa8775p_desc = {
>> };
>>
>> static const struct of_device_id gpu_cc_sa8775p_match_table[] = {
>> + { .compatible = "qcom,qcs8300-gpucc" },
>> { .compatible = "qcom,sa8775p-gpucc" },
>> { }
>> };
>> @@ -596,6 +635,14 @@ static int gpu_cc_sa8775p_probe(struct platform_device *pdev)
>> if (IS_ERR(regmap))
>> return PTR_ERR(regmap);
>>
>> + if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-gpucc")) {
>> + gpu_cc_pll0_config.l = 0x31;
>> + gpu_cc_pll0_config.alpha = 0xe555;
>> +
>> + gpu_cc_sa8775p_clocks[GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr;
>> + gpu_cc_sa8775p_clocks[GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr;
>> + }
>> +
>> clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
>> clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
>>
>>
>> --
>> 2.25.1
>>
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