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Message-ID: <20250103060035.30688-6-jianjun.wang@mediatek.com>
Date: Fri, 3 Jan 2025 14:00:15 +0800
From: Jianjun Wang <jianjun.wang@...iatek.com>
To: Bjorn Helgaas <bhelgaas@...gle.com>, Lorenzo Pieralisi
	<lpieralisi@...nel.org>, Krzysztof WilczyƄski
	<kw@...ux.com>, Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>, Rob
 Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor
 Dooley <conor+dt@...nel.org>, Matthias Brugger <matthias.bgg@...il.com>,
	AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
CC: Ryder Lee <ryder.lee@...iatek.com>, Jianjun Wang
	<jianjun.wang@...iatek.com>, <linux-pci@...r.kernel.org>,
	<linux-mediatek@...ts.infradead.org>, <devicetree@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
	Xavier Chang <Xavier.Chang@...iatek.com>
Subject: [PATCH 5/5] PCI: mediatek-gen3: Keep PCIe power and clocks if suspend-to-idle

If the target system sleep state is suspend-to-idle, the bridge is
supposed to stay in D0, and the framework will not help to restore its
configuration space, so keep its power and clocks during suspend.

It's recommended to enable L1ss support, so the link can be changed to
L1.2 state during suspend.

Signed-off-by: Jianjun Wang <jianjun.wang@...iatek.com>
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index 48f83c2d91f7..11da68910502 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -1291,6 +1291,19 @@ static int mtk_pcie_suspend_noirq(struct device *dev)
 	int err;
 	u32 val;
 
+	/*
+	 * If the target system sleep state is suspend-to-idle, the bridge is supposed to stay in
+	 * D0, and the framework will not help to restore its configuration space, so keep it's
+	 * power and clocks during suspend.
+	 *
+	 * It's recommended to enable L1ss support, so the link can be changed to L1.2 state during
+	 * suspend.
+	 */
+	if (pm_suspend_default_s2idle()) {
+		dev_info(dev, "System enter s2idle state, keep PCIe power and clocks\n");
+		return 0;
+	}
+
 	/* Trigger link to L2 state */
 	err = mtk_pcie_turn_off_link(pcie);
 	if (err) {
@@ -1316,6 +1329,11 @@ static int mtk_pcie_resume_noirq(struct device *dev)
 	struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev);
 	int err;
 
+	if (pm_suspend_default_s2idle()) {
+		dev_info(dev, "System enter s2idle state, no need to reinitialization\n");
+		return 0;
+	}
+
 	err = pcie->soc->power_up(pcie);
 	if (err)
 		return err;
-- 
2.46.0


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