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Message-ID: <CAKfKVtFNRPa64vpJ0t-ttJrp-Wc8+F2jz+Qy02BP8sgZZixsjg@mail.gmail.com>
Date: Fri, 3 Jan 2025 11:43:35 +0530
From: Shubhrajyoti Datta <shubhrajyoti.datta@...il.com>
To: Krzysztof Kozlowski <krzk@...nel.org>
Cc: Shubhrajyoti Datta <shubhrajyoti.datta@....com>, Rob Herring <robh@...nel.org>, 
	Conor Dooley <conor+dt@...nel.org>, Borislav Petkov <bp@...en8.de>, Tony Luck <tony.luck@...el.com>, 
	James Morse <james.morse@....com>, Mauro Carvalho Chehab <mchehab@...nel.org>, 
	Robert Richter <rric@...nel.org>, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-edac@...r.kernel.org, git@....com
Subject: Re: [PATCH v4 4/5] dt-bindings: memory-controllers: Add support for
 Versal NET EDAC

On Thu, Jan 2, 2025 at 11:31 PM Krzysztof Kozlowski <krzk@...nel.org> wrote:
>
> On 02/01/2025 18:44, Shubhrajyoti Datta wrote:
> > +
> > +maintainers:
> > +  - Shubhrajyoti Datta <shubhrajyoti.datta@....com>
> > +
> > +description:
> > +  The integrated DDR Memory Controllers (DDRMCs) support both DDR5 and LPDDR5
> > +  compact and extended  memory interfaces. Versal NET DDR memory controller has an optional ECC support
>
> Please wrap code according to coding style (checkpatch is not a coding
> style description, but only a tool).
Will fix .

>
>
> > +  which correct single bit ECC errors and detect double bit ECC errors.
> > +  It also has support for reporting other errors like MMCM (Mixed-Mode Clock
> > +  Manager) errors and General software errors.
> > +
> > +properties:
> > +  compatible:
> > +    const: amd,versal-net-ddrmc5-1.0
>
> 1.0 looks redundant. Usually SoC does not change... Anyway, commit msg
> should explain why 1.0 is needed (IOW, why exception is justified).
>
> > +
I will  change it to
 const: amd,versal-net-ddrmc5 instead.

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