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Message-ID: <CANAwSgS3iXUOH2_4CYK0W+A09xitDdXhQFns=E7XjwqOTUXMRg@mail.gmail.com>
Date: Sun, 5 Jan 2025 23:16:05 +0530
From: Anand Moon <linux.amoon@...il.com>
To: Niklas Cassel <cassel@...nel.org>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
Lorenzo Pieralisi <lpieralisi@...nel.org>, Krzysztof Wilczyński <kw@...ux.com>,
Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>, Heiko Stuebner <heiko@...ech.de>,
linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] PCI: dw-rockchip: Enable async probe by default
Hi Niklas,
On Fri, 3 Jan 2025 at 19:55, Niklas Cassel <cassel@...nel.org> wrote:
>
> Hello Anand,
>
> On Fri, Jan 03, 2025 at 07:24:07PM +0530, Anand Moon wrote:
> >
> > Thanks for testing this patch.
> >
> > This patch should have been tested on hardware that includes all the
> > relevant controllers,
> > such as PCI 2.0, PCI 3.0, and the SATA controller.
> > I will test this patch again on all the Radxa devices I have.
> >
> > This patch's dependency lies in deferring the probe until the PHY
> > controller initializes.
> >
> > CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m
>
>
> Note that the splat, as reported in this thread, and in:
> https://lore.kernel.org/netdev/20250101235122.704012-1-francesco@valla.it/T/
>
> is related to the network PHY (CONFIG_REALTEK_PHY) on the RTL8125 NIC,
> which is connected to one of the PCIe Gen2 controllers, not the PCIe PHY
> on the PCIe controller (CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) itself.
>
> For the record, I run with all the relevant drivers as built-in:
> CONFIG_PCIE_ROCKCHIP_DW_HOST=y
> CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y (for the PCIe Gen2 controllers)
> CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y (for the PCIe Gen3 controllers)
> CONFIG_R8169=y
> CONFIG_REALTEK_PHY=y
>
>
I am unable to reproduce this issue on my end. Could you share your
config file with me?
Additionally, if we build most of the ROCKCHIP components as modules..."
You will see this warning, which is the main reason for this patch
[ 34.642365] platform fc400000.usb: deferred probe pending: dwc3:
failed to initialize core
[ 34.642529] platform a41000000.pcie: deferred probe pending:
rockchip-dw-pcie: missing PHY
[ 34.642604] platform a40800000.pcie: deferred probe pending:
rockchip-dw-pcie: missing PHY
[ 34.642674] platform fcd00000.usb: deferred probe pending: dwc3:
failed to initialize core
> >
> > To my surprise, we have not enabled mdio on Rock-5B boards.
> > can you check if these changes work on your end?
>
> I think these changes are wrong, at least for rock5b.
>
> On rock5b the RTL8125 NIC is connected via PCI, and PCI devices should not
> be specified in device tree, as PCI is a bus that can be enumerated.
>
According to RK3588 (TRM) documentation specifies the requirement for
a dedicated GMAC controller
to effectively manage certain critical network features. In the
absence of this specialized controller,
the network interface card (NIC) may operate solely as a standard PCIe
NIC, potentially leading to
suboptimal performance and a lack of robust flow control mechanisms.
Log analysis indicates that Ethernet probing occurs before the
initialization of the PCIe PHY and PCIe hosts.
To investigate this issue, please test with the following configuration changes:
1 Set CONFIG_DWMAC_ROCKCHIP=m.
2 Enable the probe mode PROBE_PREFER_ASYNCHRONOUS for the DWMAC_ROCKCHIP driver.
Thanks
-Anand
>
> >
> > -----8<----------8<----------8<----------8<----------8<----------8<-----
> > alarm@...k-5b:/media/nvme0/mainline/linux-rockchip-6.y-devel$ git diff
> > arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
> > b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
> > index c44d001da169..5008a05efd2a 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
> > +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
> > @@ -155,6 +155,19 @@ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
> > };
> > };
> >
> > +&mdio1 {
> > + rgmii_phy1: ethernet-phy@1 {
> > + /* RTL8211F */
> > + compatible = "ethernet-phy-id001c.c916";
> > + reg = <0x1>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&rtl8211f_rst>;
> > + reset-assert-us = <20000>;
> > + reset-deassert-us = <100000>;
> > + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
> > + };
> > +};
> > +
> > &combphy0_ps {
> > status = "okay";
> > };
> > @@ -224,6 +237,21 @@ &hdptxphy_hdmi0 {
> > status = "okay";
> > };
> >
> > +&gmac1 {
> > + clock_in_out = "output";
> > + phy-handle = <&rgmii_phy1>;
> > + phy-mode = "rgmii";
> > + pinctrl-0 = <&gmac1_miim
> > + &gmac1_tx_bus2
> > + &gmac1_rx_bus2
> > + &gmac1_rgmii_clk
> > + &gmac1_rgmii_bus>;
> > + pinctrl-names = "default";
> > + tx_delay = <0x3a>;
> > + rx_delay = <0x3e>;
> > + status = "okay";
> > +};
> > +
> > &i2c0 {
> > pinctrl-names = "default";
> > pinctrl-0 = <&i2c0m2_xfer>;
> > @@ -419,6 +447,12 @@ pcie3_vcc3v3_en: pcie3-vcc3v3-en {
> > };
> > };
> >
> > + rtl8211f {
> > + rtl8211f_rst: rtl8211f-rst {
> > + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
> > + };
> > + };
> > +
> > usb {
> > vcc5v0_host_en: vcc5v0-host-en {
> > rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
> > >
> > > Kind regards,
> > > Niklas
> >
> > Can you check this on your end
> >
> > alarm@...k-5b:~$ sudo cat /sys/kernel/debug/devices_deferred
> > [sudo] password for alarm:
> > fc400000.usb dwc3: failed to initialize core
> > alarm@...k-5b:~$ sudo cat /sys/kernel/debug/devices_deferred
>
> Sure:
> # cat /sys/kernel/debug/devices_deferred
> fc400000.usb dwc3: failed to initialize core
>
>
> Kind regards,
> Niklas
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