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Message-ID: <CA+V-a8tYphwwTqzzwH+0kBGLGZZYLW+eiJsHpe-cvpywMRnEaA@mail.gmail.com>
Date: Mon, 6 Jan 2025 20:33:06 +0000
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>, Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>
Cc: linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH] clk: renesas: rzg2l-cpg: Refactor Runtime PM clock validation
Hi Geert,
On Mon, Dec 16, 2024 at 9:02 PM Prabhakar <prabhakar.csengg@...il.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Refactor rzg2l_cpg_attach_dev to delegate clock validation for Runtime PM
> to the updated rzg2l_cpg_is_pm_clk function. Ensure validation of clocks
> associated with the power domain while excluding external and core clocks.
> Prevent incorrect Runtime PM management for clocks outside the domain's
> scope.
>
> Update rzg2l_cpg_is_pm_clk to operate on a per-power-domain basis. Verify
> clkspec.np against the domain's device node, check argument validity, and
> validate clock type (CPG_MOD). Use the no_pm_mod_clks array to exclude
> specific clocks from PM management.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> ---
> drivers/clk/renesas/rzg2l-cpg.c | 102 +++++++++++++++++---------------
> 1 file changed, 54 insertions(+), 48 deletions(-)
>
Gentle ping.
Cheers,
Prabhakar
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