linux-kernel - [PATCH v5 5/5] x86/cpufeatures: Add the CPU feature bit for MSR immediate form instructions

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Message-ID: <20250106070727.3211006-6-xin@zytor.com>
Date: Sun,  5 Jan 2025 23:07:27 -0800
From: "Xin Li (Intel)" <xin@...or.com>
To: linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org
Cc: tglx@...utronix.de, mingo@...hat.com, bp@...en8.de,
        dave.hansen@...ux.intel.com, x86@...nel.org, hpa@...or.com,
        will@...nel.org, peterz@...radead.org, yury.norov@...il.com,
        akpm@...ux-foundation.org, acme@...nel.org, namhyung@...nel.org,
        brgerst@...il.com, andrew.cooper3@...rix.com, nik.borisov@...e.com
Subject: [PATCH v5 5/5] x86/cpufeatures: Add the CPU feature bit for MSR immediate form instructions

The immediate form of MSR access instructions are primarily motivated by
performance, not code size: by having the MSR number in an immediate, it
is available *much* earlier in the pipeline, which allows the hardware
much more leeway about how a particular MSR is handled.

Add a new CPU feature word for CPUID.7.1.ECX and then the CPU feature bit
for MSR immediate form.

Signed-off-by: Xin Li (Intel) <xin@...or.com>
---
 arch/x86/include/asm/cpufeature.h  | 1 +
 arch/x86/include/asm/cpufeatures.h | 5 ++++-
 arch/x86/kernel/cpu/common.c       | 1 +
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index b829a12eda8a..9a2991e7b21b 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -35,6 +35,7 @@ enum cpuid_leafs
 	CPUID_8000_001F_EAX,
 	CPUID_8000_0021_EAX,
 	CPUID_LNX_5,
+	CPUID_7_1_ECX,
 	NR_CPUID_WORDS,
 };
 
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index d5985e8eef29..59aa04915032 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -5,7 +5,7 @@
 /*
  * Defines x86 CPU feature bits
  */
-#define NCAPINTS			22	   /* N 32-bit words worth of info */
+#define NCAPINTS			23	   /* N 32-bit words worth of info */
 #define NBUGINTS			2	   /* N 32-bit bug flags */
 
 /*
@@ -476,6 +476,9 @@
 #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */
 #define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /* Workload Classification */
 
+/* Intel-defined CPU features, CPUID level 0x00000007:1 (ECX), word 22 */
+#define X86_FEATURE_MSR_IMM		(22*32+ 5) /* "msr_imm" MSR immediate form instructions */
+
 /*
  * BUG word(s)
  */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 7cce91b19fb2..13d270eabd09 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -997,6 +997,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
 		if (eax >= 1) {
 			cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
 			c->x86_capability[CPUID_7_1_EAX] = eax;
+			c->x86_capability[CPUID_7_1_ECX] = ecx;
 		}
 	}
 
-- 
2.47.1