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Message-ID: <a110be11-923e-4943-8741-43b5513c9691@ghiti.fr>
Date: Mon, 6 Jan 2025 11:31:45 +0100
From: Alexandre Ghiti <alex@...ti.fr>
To: guoren@...nel.org, tjeznach@...osinc.com
Cc: joro@...tes.org, will@...nel.org, robin.murphy@....com,
paul.walmsley@...ive.com, palmer@...belt.com, baolu.lu@...ux.intel.com,
zong.li@...ive.com, iommu@...ts.linux.dev, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, Guo Ren <guoren@...ux.alibaba.com>
Subject: Re: [PATCH] iommu/riscv: Fixup compile warning
Hi Guo,
On 03/01/2025 03:46, guoren@...nel.org wrote:
> From: Guo Ren <guoren@...ux.alibaba.com>
>
> When __BITS_PER_LONG == 32, size_t is defined as unsigned int rather
RISCV_IOMMU depends on 64BIT so how do you get __BITS_PER_LONG == 32?
Thanks,
Alex
> than unsigned long. Therefore, we should use size_t to avoid
> type-checking errors.
>
> Fixes: 488ffbf18171 ("iommu/riscv: Paging domain support")
> Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@...nel.org>
> Cc: Tomasz Jeznach <tjeznach@...osinc.com>
> ---
> drivers/iommu/riscv/iommu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
> index 8a05def774bd..38d381164385 100644
> --- a/drivers/iommu/riscv/iommu.c
> +++ b/drivers/iommu/riscv/iommu.c
> @@ -1270,7 +1270,7 @@ static phys_addr_t riscv_iommu_iova_to_phys(struct iommu_domain *iommu_domain,
> dma_addr_t iova)
> {
> struct riscv_iommu_domain *domain = iommu_domain_to_riscv(iommu_domain);
> - unsigned long pte_size;
> + size_t pte_size;
> unsigned long *ptr;
>
> ptr = riscv_iommu_pte_fetch(domain, iova, &pte_size);
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