linux-kernel - Re: [PATCH 11/12] x86/mm: enable AMD translation cache extensions

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Message-ID: <CAG48ez3aLwOW+jpJbLB-vXGudLQnDLCYs=Ao3eNikv6QiTc1Fw@mail.gmail.com>
Date: Mon, 6 Jan 2025 14:10:11 +0100
From: Jann Horn <jannh@...gle.com>
To: Rik van Riel <riel@...riel.com>, Sean Christopherson <seanjc@...gle.com>, 
	Paolo Bonzini <pbonzini@...hat.com>, KVM list <kvm@...r.kernel.org>, 
	Tom Lendacky <thomas.lendacky@....com>
Cc: x86@...nel.org, linux-kernel@...r.kernel.org, kernel-team@...a.com, 
	dave.hansen@...ux.intel.com, luto@...nel.org, peterz@...radead.org, 
	tglx@...utronix.de, mingo@...hat.com, bp@...en8.de, hpa@...or.com, 
	akpm@...ux-foundation.org, nadav.amit@...il.com, zhengqi.arch@...edance.com, 
	linux-mm@...ck.org
Subject: Re: [PATCH 11/12] x86/mm: enable AMD translation cache extensions

+KVM/SVM folks in case they know more about how enabling CPU features
interacts with virtualization; original patch is at
https://lore.kernel.org/all/20241230175550.4046587-12-riel@surriel.com/

On Sat, Jan 4, 2025 at 4:08 AM Rik van Riel <riel@...riel.com> wrote:
> On Fri, 2025-01-03 at 18:49 +0100, Jann Horn wrote:
> > On Mon, Dec 30, 2024 at 6:53 PM Rik van Riel <riel@...riel.com>
> > > only those upper-level entries that lead to the target PTE in
> > > the page table hierarchy, leaving unrelated upper-level entries
> > > intact.
> >
> > How does this patch interact with KVM SVM guests?
> > In particular, will this patch cause TLB flushes performed by guest
> > kernels to behave differently?
> >
> That is a good question.
>
> A Linux guest should be fine, since Linux already
> flushes the parts of the TLB where page tables are
> being freed.
>
> I don't know whether this could potentially break
> some non-Linux guests, though.