linux-kernel - [PATCH v2 0/2] Enable PCIe Multilink and USB support in Cadence Torrent SERDES driver

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Message-ID: <20250106131925.263240-1-s-vadapalli@ti.com>
Date: Mon, 6 Jan 2025 18:49:16 +0530
From: Siddharth Vadapalli <s-vadapalli@...com>
To: <vkoul@...nel.org>, <kishon@...nel.org>, <sjakhade@...ence.com>,
        <rogerq@...nel.org>, <thomas.richard@...tlin.com>,
        <christophe.jaillet@...adoo.fr>, <u.kleine-koenig@...libre.com>,
        <eballetb@...hat.com>
CC: <linux-phy@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>, <srk@...com>,
        <s-vadapalli@...com>
Subject: [PATCH v2 0/2] Enable PCIe Multilink and USB support in Cadence Torrent SERDES driver

Hello,

This series adds support for standalone PCIe Multilink configuration
along with the support for PCIe Multilink + USB configuration in the
Torrent SERDES driver.

Series is based on linux-next tagged next-20250106.

v1:
https://lore.kernel.org/r/20240615093433.3659829-1-s-vadapalli@ti.com/
Changes since v1:
- Rebased series on next-20250106.
- Significant changes have been made in the second patch of the series
  in the process of rebasing. Support for 3 or more links was introduced
  and this series had to be modified to be compatible with those changes.
- Added "Co-developed-by" tag in the second patch since some of the
  changes in this series in the process of rebasing were made by me
  which are quite different from the v1 version of the patch.
- Due to these changes, I have *not* collected the "Tested-by" tag on the
  v1 series from Enric Balletbo i Serra <eballetbo@...hat.com>
  and I hope that this series can be tested.

I have sanity tested this series on AM69-SK, validating the following:
- Boot
- SERDES0 PLLs being locked for PCIe Multilink + USB configuration:
  PCIe1 x2 -> Lanes 0 and 1 of SERDES0 -> Link 1 (Subnode 1)
  PCIe3 x1 -> Lane 2 of SERDES0 -> Link 2 (Subnode 2)
  USB -> Lane 3 of SERDES0 -> Link 3 (Subnode 3)

***NOTE***
Since I don't have the hardware required to validate PCIe Multilink +
USB functionality, kindly *do not merge* this series until it gets a
"Tested-by" tag with proper validation of the functionality.

Regards,
Siddharth.

Swapnil Jakhade (2):
  phy: cadence-torrent: Add PCIe multilink configuration for 100 MHz
    refclk
  phy: cadence-torrent: Add PCIe multilink + USB with same SSC register
    config for 100 MHz refclk

 drivers/phy/cadence/phy-cadence-torrent.c | 288 +++++++++++++++++++++-
 1 file changed, 279 insertions(+), 9 deletions(-)

-- 
2.43.0