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Message-ID: <8b7b0d1bca5088bda46a651481b9a42f3be1a75d.camel@mediatek.com>
Date: Tue, 7 Jan 2025 02:44:37 +0000
From: Jianjun Wang (王建军) <Jianjun.Wang@...iatek.com>
To: "helgaas@...nel.org" <helgaas@...nel.org>
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<krzk+dt@...nel.org>, AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>, Ryder Lee <Ryder.Lee@...iatek.com>
Subject: Re: [PATCH 3/5] PCI: mediatek-gen3: Disable ASPM L0s
On Fri, 2025-01-03 at 13:15 -0600, Bjorn Helgaas wrote:
> External email : Please do not click links or open attachments until
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>
> On Fri, Jan 03, 2025 at 02:00:13PM +0800, Jianjun Wang wrote:
> > Disable ASPM L0s support because it does not significantly save
> > power
> > but impacts performance.
>
> This seems like a user/administrator decision, not a driver decision.
>
> L0s reduces power at the cost of performance for *all* PCIe devices,
> although the actual numbers may vary.
We have encountered some compatibility issues when connected with some
PCIe EPs, these issues are probabilistic and disabling the L0s can fix
them.
Users may not be aware of these issues, so I think disabling L0s
through the driver might be the better way, since it does not
significantly save power and we usually use L1ss for power-saving when
the link is idle.
Thanks.
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