linux-kernel - Re: [PATCH 3/5] PCI: mediatek-gen3: Disable ASPM L0s

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Message-ID: <20250107230742.GA189563@bhelgaas>
Date: Tue, 7 Jan 2025 17:07:42 -0600
From: Bjorn Helgaas <helgaas@...nel.org>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Cc: Jianjun Wang (王建军) <Jianjun.Wang@...iatek.com>,
	"manivannan.sadhasivam@...aro.org" <manivannan.sadhasivam@...aro.org>,
	"conor+dt@...nel.org" <conor+dt@...nel.org>,
	"robh@...nel.org" <robh@...nel.org>, "kw@...ux.com" <kw@...ux.com>,
	"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
	"matthias.bgg@...il.com" <matthias.bgg@...il.com>,
	"krzk+dt@...nel.org" <krzk+dt@...nel.org>,
	"lpieralisi@...nel.org" <lpieralisi@...nel.org>,
	"linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	"linux-mediatek@...ts.infradead.org" <linux-mediatek@...ts.infradead.org>,
	Ryder Lee <Ryder.Lee@...iatek.com>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	Xavier Chang (張獻文) <Xavier.Chang@...iatek.com>
Subject: Re: [PATCH 3/5] PCI: mediatek-gen3: Disable ASPM L0s

On Tue, Jan 07, 2025 at 12:44:43PM +0100, AngeloGioacchino Del Regno wrote:
> Il 07/01/25 03:18, Jianjun Wang (王建军) ha scritto:
> > On Fri, 2025-01-03 at 10:16 +0100, AngeloGioacchino Del Regno wrote:
> > > Il 03/01/25 07:00, Jianjun Wang ha scritto:
> > > > Disable ASPM L0s support because it does not significantly save
> > > > power
> > > > but impacts performance.
> > > 
> > > That may be a good idea but, without numbers to support your
> > > statement, it's a bit
> > > difficult to say.
> > > 
> > > How much power does ASPM L0s save on MediaTek SoCs, in microwatts?
> > > How is the performance impacted, and on which specific device(s) on
> > > the PCIe bus?
> > 
> > It's hard to tell the exact number because it is difficult to measure,
> > and the number of entries into the L0s state may vary even in the same
> > test scenario.
> > 
> > However, we have encountered some compatibility issues when connected
> > with some PCIe EPs, and disabling the L0s can fix it. I think disabling
> > L0s might be the better way, since we usually use L1ss for power-saving
> > when the link is idle.
> 
> To actually decide, we should know what's actually broken, then.
> 
> Is the MediaTek controller broken, or is the device broken?
> So, is it a MTK quirk, or a device quirk?
> 
> If the problem is actually device-related, then this should be handled as
> a device-specific quirk, as not just MediaTek platforms would be affected
> by compatibility issues.
> 
> If the MediaTek PCIe controller is at fault, instead, I agree about just
> disabling L0s at the controller level - but then this shall be mentioned
> in the commit message, and should have a Fixes tag as well.

100% agreed, sorry for repeating what you just said before I finished
reading the thread!

Bjorn