linux-kernel - [RFC PATCH 0/8] Delay to enumerate ports/dports component registers

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Message-Id: <20250107035708.1134954-1-ming.li@zohomail.com>
Date: Tue,  7 Jan 2025 11:57:00 +0800
From: Li Ming <ming.li@...omail.com>
To: dave@...olabs.net,
	jonathan.cameron@...wei.com,
	dave.jiang@...el.com,
	alison.schofield@...el.com,
	vishal.l.verma@...el.com,
	ira.weiny@...el.com,
	dan.j.williams@...el.com
Cc: linux-cxl@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Li Ming <ming.li@...omail.com>
Subject: [RFC PATCH 0/8] Delay to enumerate ports/dports component registers

This patchset implements the long term fix for the locating CXL.CM
capability failure issue[1].

In some hardware platform, CXL capable ports and dports will not expose
component registers if they are not working on CXL mode, but CXL
subsystem always enumerates component registers on a CXL port/dport
during it is added to the hierarchy. It causes component registers
enumeration failure on a CXL port or CXL dport if no CXL device is
under it when the CXL port or CXL dport is attaching to the hierarchy.
It will be a problem on the environment with CXL hotplug support.

The solution in this patchset is that moving port and dport component
registers enumeration from devm_cxl_add_port()/devm_cxl_add_dport() into
cxl_endpoint_port_probe(), delaying port and dport component registers
enumeration until the first endpoint port probing. When the first
endpoint port is probing, it represents ancestor ports and dports are
working on CXL mode.

To support this solution, extra changes are needed in this patchset:
1. Ancestor ports' HDM initialization also needs to be moved from
cxl_switch_port_probe() to cxl_endpoint_port_probe(), because HDM
initialization should be done after component registers are ready.

2. Remove ancestor ports' HDM and reset ancestor ports and dports'
component registers information when the last endpoint of the hierarchy
detaching, so that the first endpoint attaching can enumerate ancestor
ports and dports' component registers and set up HDM on ancestor ports
next time.

base-commit: 4bbf9020becbfd8fc2c3da790855b7042fad455b v6.13-rc4 
[1] https://lore.kernel.org/linux-cxl/59EA939D-03E1-40FC-88D2-BCFA4DE5A436@suse.de/

Li Ming (8):
  cxl/port: Enumerate port component regs when endpoint attaching
  cxl/port: Delay port HDM setup until port component regs setup done
  cxl/region: Check if dev is a decoder in check_commit_order()
  cxl/port: Remove port HDM during the last endpoint detaching
  cxl/port: Remove component_reg_phys parameter from devm_cxl_add_port()
  cxl/port: Enumerate dport component registers when endpoint attaching
  cxl/port: Remove component_reg_phys parameter from
    devm_cxl_add_dport()
  cxl/mem: Adjust cxl_dport_init_ras_reporting() invoked position

 drivers/cxl/acpi.c            |   6 +-
 drivers/cxl/core/pci.c        |   8 +-
 drivers/cxl/core/port.c       | 229 +++++++++++++++++++++-------------
 drivers/cxl/core/region.c     |   8 +-
 drivers/cxl/cxl.h             |  10 +-
 drivers/cxl/mem.c             |   7 +-
 drivers/cxl/port.c            |  40 +++++-
 tools/testing/cxl/test/cxl.c  |   4 +-
 tools/testing/cxl/test/mock.c |   3 +-
 9 files changed, 206 insertions(+), 109 deletions(-)

-- 
2.34.1