linux-kernel - [RFC PATCH 5/8] cxl/port: Remove component_reg_phys parameter from devm_cxl_add

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Message-Id: <20250107035708.1134954-6-ming.li@zohomail.com>
Date: Tue,  7 Jan 2025 11:57:05 +0800
From: Li Ming <ming.li@...omail.com>
To: dave@...olabs.net,
	jonathan.cameron@...wei.com,
	dave.jiang@...el.com,
	alison.schofield@...el.com,
	vishal.l.verma@...el.com,
	ira.weiny@...el.com,
	dan.j.williams@...el.com
Cc: linux-cxl@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Li Ming <ming.li@...omail.com>
Subject: [RFC PATCH 5/8] cxl/port: Remove component_reg_phys parameter from devm_cxl_add_port()

devm_cxl_add_port() is not responsible for port component registers
setup anymore, the component_reg_phys parameter is unnecessary for
devm_cxl_add_port().

Signed-off-by: Li Ming <ming.li@...omail.com>
---
 drivers/cxl/acpi.c      |  3 ++-
 drivers/cxl/core/port.c | 19 +++++--------------
 drivers/cxl/cxl.h       |  1 -
 drivers/cxl/mem.c       |  3 +--
 4 files changed, 8 insertions(+), 18 deletions(-)

diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index cb14829bb9be..b754c2c55659 100644
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -662,9 +662,10 @@ static int add_host_bridge_uport(struct device *match, void *arg)
 	if (rc)
 		return rc;
 
-	port = devm_cxl_add_port(host, bridge, component_reg_phys, dport);
+	port = devm_cxl_add_port(host, bridge, dport);
 	if (IS_ERR(port))
 		return PTR_ERR(port);
+	port->chbcr = component_reg_phys;
 
 	dev_info(bridge, "host supports CXL\n");
 
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 57ed152d96d7..b406ba64f6bc 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -873,9 +873,7 @@ static void cxl_debugfs_create_dport_dir(struct cxl_dport *dport)
 			    &cxl_einj_inject_fops);
 }
 
-static int cxl_port_add(struct cxl_port *port,
-			resource_size_t component_reg_phys,
-			struct cxl_dport *parent_dport)
+static int cxl_port_add(struct cxl_port *port, struct cxl_dport *parent_dport)
 {
 	struct device *dev __free(put_device) = &port->dev;
 	int rc;
@@ -900,9 +898,6 @@ static int cxl_port_add(struct cxl_port *port,
 		rc = dev_set_name(dev, "port%d", port->id);
 		if (rc)
 			return rc;
-
-		if (is_cxl_root(parent_dport->port))
-			port->chbcr = component_reg_phys;
 	} else {
 		rc = dev_set_name(dev, "root%d", port->id);
 		if (rc)
@@ -920,7 +915,6 @@ static int cxl_port_add(struct cxl_port *port,
 
 static struct cxl_port *__devm_cxl_add_port(struct device *host,
 					    struct device *uport_dev,
-					    resource_size_t component_reg_phys,
 					    struct cxl_dport *parent_dport)
 {
 	struct cxl_port *port;
@@ -930,7 +924,7 @@ static struct cxl_port *__devm_cxl_add_port(struct device *host,
 	if (IS_ERR(port))
 		return port;
 
-	rc = cxl_port_add(port, component_reg_phys, parent_dport);
+	rc = cxl_port_add(port, parent_dport);
 	if (rc)
 		return ERR_PTR(rc);
 
@@ -956,18 +950,15 @@ static struct cxl_port *__devm_cxl_add_port(struct device *host,
  * devm_cxl_add_port - register a cxl_port in CXL memory decode hierarchy
  * @host: host device for devm operations
  * @uport_dev: "physical" device implementing this upstream port
- * @component_reg_phys: (optional) for configurable cxl_port instances
  * @parent_dport: next hop up in the CXL memory decode hierarchy
  */
 struct cxl_port *devm_cxl_add_port(struct device *host,
 				   struct device *uport_dev,
-				   resource_size_t component_reg_phys,
 				   struct cxl_dport *parent_dport)
 {
 	struct cxl_port *port, *parent_port;
 
-	port = __devm_cxl_add_port(host, uport_dev, component_reg_phys,
-				   parent_dport);
+	port = __devm_cxl_add_port(host, uport_dev, parent_dport);
 
 	parent_port = parent_dport ? parent_dport->port : NULL;
 	if (IS_ERR(port)) {
@@ -994,7 +985,7 @@ struct cxl_root *devm_cxl_add_root(struct device *host,
 	struct cxl_root *cxl_root;
 	struct cxl_port *port;
 
-	port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL);
+	port = devm_cxl_add_port(host, host, NULL);
 	if (IS_ERR(port))
 		return ERR_CAST(port);
 
@@ -1661,7 +1652,7 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd,
 		port = find_cxl_port_at(parent_port, dport_dev, &dport);
 		if (!port) {
 			port = devm_cxl_add_port(&parent_port->dev, uport_dev,
-						 CXL_RESOURCE_NONE, parent_dport);
+						 parent_dport);
 			if (IS_ERR(port))
 				return PTR_ERR(port);
 
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 9877a0ddb5e9..7763be02ef81 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -748,7 +748,6 @@ int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev,
 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port);
 struct cxl_port *devm_cxl_add_port(struct device *host,
 				   struct device *uport_dev,
-				   resource_size_t component_reg_phys,
 				   struct cxl_dport *parent_dport);
 struct cxl_root *devm_cxl_add_root(struct device *host,
 				   const struct cxl_root_ops *ops);
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
index 2f03a4d5606e..39da99a4bf4d 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/mem.c
@@ -65,8 +65,7 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
 	}
 
 	/* Note: endpoint port component registers are derived from @cxlds */
-	endpoint = devm_cxl_add_port(host, &cxlmd->dev, CXL_RESOURCE_NONE,
-				     parent_dport);
+	endpoint = devm_cxl_add_port(host, &cxlmd->dev, parent_dport);
 	if (IS_ERR(endpoint))
 		return PTR_ERR(endpoint);
 
-- 
2.34.1