lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <hrtwoxi6ib7obmijhe4rlrpppgcybhp44w3mhjg7d4ovbrfnv4@qyjt57fuj3o6>
Date: Tue, 7 Jan 2025 07:54:20 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Rohit Visavalia <rohit.visavalia@....com>
Cc: mturquette@...libre.com, sboyd@...nel.org, robh@...nel.org, 
	krzk+dt@...nel.org, conor+dt@...nel.org, vishal.sagar@....com, michal.simek@....com, 
	linux-clk@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 2/2] dt-bindings: clock: xilinx: Add reset GPIO for VCU

On Mon, Jan 06, 2025 at 08:40:38PM -0800, Rohit Visavalia wrote:
> It is marked as optional as some of the ZynqMP designs are having vcu_reset
> (reset pin of VCU IP) driven by proc_sys_reset, proc_sys_reset is another
> PL IP driven by the PS pl_reset. So, here the VCU reset is not driven by
> axi_gpio or PS GPIO so there will be no GPIO entry.
> 
> Signed-off-by: Rohit Visavalia <rohit.visavalia@....com>
> ---
> Changes in v2:
>   - dropped description GPIO property
>   - used decimal number for GPIO
> 

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>

Best regards,
Krzysztof


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ