[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <rqezansr45u4qu6xmrmqtugi5y2tjfuq4embv6ofeoatmc6be4@4lzsywehfk63>
Date: Mon, 6 Jan 2025 18:52:26 -0600
From: Bjorn Andersson <andersson@...nel.org>
To: Abhinav Kumar <quic_abhinavk@...cinc.com>
Cc: Rob Clark <robdclark@...il.com>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>, Sean Paul <sean@...rly.run>,
Marijn Suijten <marijn.suijten@...ainline.org>, David Airlie <airlied@...il.com>,
Simona Vetter <simona@...ll.ch>, Stephen Boyd <swboyd@...omium.org>,
Chandan Uddaraju <chandanu@...eaurora.org>, Guenter Roeck <groeck@...omium.org>,
Kuogee Hsieh <quic_khsieh@...cinc.com>, Konrad Dybcio <konradybcio@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Vara Reddy <quic_varar@...cinc.com>,
Rob Clark <robdclark@...omium.org>, Tanmay Shah <tanmay@...eaurora.org>,
linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
Jessica Zhang <quic_jesszhan@...cinc.com>, Laurent Pinchart <laurent.pinchart@...asonboard.com>,
Yongxing Mou <quic_yongmou@...cinc.com>
Subject: Re: [PATCH 44/45] arm64: dts: qcom: add mst support for pixel stream
clk for DP0
On Thu, Dec 05, 2024 at 08:32:15PM -0800, Abhinav Kumar wrote:
> From: Yongxing Mou <quic_yongmou@...cinc.com>
>
I'd expect "sa8775p" in the subject prefix.
> Populate the pixel clock for stream 1 for DP0 for sa8775p DP controller.
Please write your commit messages in the style expressed in
https://docs.kernel.org/process/submitting-patches.html#describe-your-changes
Use the commit message to document why the code/dt looks like it does.
Describe the problem your solving and why.
>
> Signed-off-by: Yongxing Mou <quic_yongmou@...cinc.com>
> Signed-off-by: Abhinav Kumar <quic_abhinavk@...cinc.com>
> ---
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 0dbaa17e5e3f06c61b2aa777e45b73a48e50e66b..0150ce27b98e9894fa9ee6cccd020528d716f543 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -3944,16 +3944,20 @@ mdss0_dp0: displayport-controller@...4000 {
> <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
> <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
> <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
> clock-names = "core_iface",
> "core_aux",
> "ctrl_link",
> "ctrl_link_iface",
> - "stream_pixel";
> + "stream_pixel",
> + "stream_1_pixel";
I don't see this being a valid clock-names in the DT binding, does this
pass dtbs_check?
Regards,
Bjorn
> assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> - assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
> + assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>, <&mdss0_dp0_phy 1>;
> phys = <&mdss0_dp0_phy>;
> +
> phy-names = "dp";
>
> operating-points-v2 = <&dp_opp_table>;
>
> --
> 2.34.1
>
Powered by blists - more mailing lists