linux-kernel - RE: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID:
 <TY3PR01MB11346E9B6CD4CDB6EF93B99C986112@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Tue, 7 Jan 2025 12:38:20 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
CC: Geert Uytterhoeven <geert+renesas@...der.be>, Michael Turquette
	<mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
	"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, Fabrizio
 Castro <fabrizio.castro.jz@...esas.com>, Prabhakar Mahadev Lad
	<prabhakar.mahadev-lad.rj@...renesas.com>
Subject: RE: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to
 per-bit basis

Hi Prabhakar,

> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@...il.com>
> Sent: 07 January 2025 12:31
> Subject: Re: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis
> 
> Hi Biju,
> 
> On Tue, Jan 7, 2025 at 12:25 PM Biju Das <biju.das.jz@...renesas.com> wrote:
> >
> > Hi Prabhakar,
> >
> > > -----Original Message-----
> > > From: Lad, Prabhakar <prabhakar.csengg@...il.com>
> > > Sent: 07 January 2025 11:46
> > > Subject: Re: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP
> > > configuration to per-bit basis
> > >
> > > Hi Biju,
> > >
> > > On Tue, Jan 7, 2025 at 11:24 AM Biju Das <biju.das.jz@...renesas.com> wrote:
> > > >
> > > > Hi Prabhakar,
> > > >
> > > > Thanks for the patch.
> > > >
> > > > > -----Original Message-----
> > > > > From: Prabhakar <prabhakar.csengg@...il.com>
> > > > > Sent: 02 January 2025 18:19
> > > > > Subject: [PATCH v3 4/6] clk: renesas: rzv2h: Switch MSTOP
> > > > > configuration to per-bit basis
> > > > >
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > > > >
> > > > > Switch MSTOP handling from group-based to per-bit configuration
> > > > > to address issues with shared dependencies between module
> > > > > clocks. In the current group-based configuration, multiple
> > > > > module clocks may rely on a single MSTOP bit. When both clocks
> > > > > are turned ON and one is subsequently turned OFF, the shared
> > > > > MSTOP bit will still be set, which is incorrect since the
> > > other dependent module clock remains ON.
> > > >
> > > > I guess this statement is incorrect. Still in group-based, mstop
> > > > bit is controlled by usage
> > > count(ref_cnt).
> > > >
> > > It is valid, consider an example say IP-A reuiqres MSTOP bits 8 | 9
> > > |
> > > 10 and consider IP-B requires MSTOP bits 10 | 11 | 12 (of the same
> > > MSTOP register say MSTOP1). Now this will be seperate groups having
> > > separate count(ref_cnt). Say you turn ON IP-A module clock and
> > > correspondingly clear the MSTOP bits and similarly now lets turn ON
> > > module clocks for IP-B and clear the MSTOP bits. Now let's say you
> > > want to turn OFF IP-A so you turn OFF module clock and set the MSTOP bits 8 | 9 | 10. In this case
> you will now see issues with IP-B as MSTOP BIT(10) has been set when we turned OFF IP-A block.  This
> case is handled by switching refcount on per mstop bit by this patch.
> >
> > I agree, Do we have such use case?
> >
> Yes, for USB2.0 on RZ/V2H.

OK, then it make sense for per-bit configuration.

> 
> > Consider another use case, index 0, bit 8| index 0, bit9| index0, bit10 and index 0, bit8 | index1,
> bit 0 | index1 10 is addressed in current patch series?
> >
> Can you please elaborate, the above isn't clear to me.


I just provide a random example for a future IP, where

IP_A requires mstop1 {8,9,10}
And
IP_B requires mstop1 {8} and mstop2 {9, 10}

Note: I haven't seen this scenario in hardware manual.


Cheers,
Biju